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Erschienen in:
2004 | OriginalPaper | Buchkapitel
Accurate Cache and TLB Characterization Using Hardware Counters
verfasst von : Jack Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, Haihang You
Erschienen in: Computational Science - ICCS 2004
Verlag: Springer Berlin Heidelberg
Enthalten in: Professional Book Archive
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We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions.