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2000 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

Computer Architecture

Complexity and Correctness

verfasst von: Silvia Melitta Mueller, Wolfgang J. Paul

Verlag: Springer Berlin Heidelberg

Enthalten in: Professional Book Archive

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Über dieses Buch

Computer Architecture: Complexity and Correctness develops, at the gate level, the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. In contrast to other design approaches applied in practice and unlike other textbooks available, the design presented here are modular, clean and complete up to the construction of entire complex machines. The authors' systematically basing their approach on rigorous mathematical formalisms allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation as well as, generally speaking, for coverage of a broad variety of relevant issues within a reasonable number of pages. The book is written as a text for classes on computer architecture and related topics and will serve as a valuable source of reference for professionals in hardware design.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
In this book we develop at the gate level the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit.
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 2. Basics
Abstract
STUDYING COMPUTER architecture without counting the cost of hardware and the length of critical paths is great fun. It is like going shopping without looking at price tags at all. In this book, we specify and analyze hardware in the model from [MP95]. This is a model at the gate level which gives at least rough price tags.
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 3. A Sequential DLX Design
Abstract
IN THE remainder of this book we develop a pipelined DLX machine with precise interrupts, caches and an IEEE-compliant floating point unit. Starting point of our designs is a sequential DLX machine without interrupt processing, caches and floating point unit. The cost effectiveness of later designs will be compared with the cost effectiveness of this basic machine.
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 4. Basic Pipelining
Abstract
IN THE CPU constructed in the previous chapter DLX instructions are processed sequentially, this means that the processing of an instruction starts only after the processing of the previous instruction is completed. The processing of an instruction takes between 3 and 5 cycles. Most of the hardware of the CPU is idle most of the time. One therefore tries to re-schedule the use of the hardware resources such that several instructions can be processed simultaneously. Obviously, the following conditions should be fulfilled:
1.
No structural hazards exist, i.e., at no time, any hardware resource is used by two instructions simultaneously.
 
2.
The machine is correct, i.e., the hardware interprets the instruction set.
 
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 5. Interrupt Handling
Abstract
Interrupts ARE events, which change the flow of control of a program by means other than a branch instruction. They are triggered by the activation of event signals, which we denote by ev[j], j = 0,1,.... Here, we will consider the interrupts shown in table 5.1.
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 6. Memory System Design
Abstract
ONE WAY to improve the performance of an architecture, is trying to increase the instruction throughput, for example by pipelining, but that calls for a fast memory system, as the analysis of section 4.6.5 has turned out.
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 7. IEEE Floating Point Standard and Theory of Rounding
Abstract
IN THIS chapter, we introduce the algebra needed to talk concisely about floating point circuits and to argue about their correctness. In this formalism, we specify parts of the IEEE floating point standard [Ins85], and we derive basic properties of IEEE-compliant floating point algorithms. Two issues will be of central interest: the number representation and the rounding.
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 8. Floating Point Algorithms and Data Paths
Abstract
IN THIS chapter the data paths of an IEEE-compatible floating point unit FPU are developed. The unit is depicted in figure 8.2. It is capable of handling single and double precision numbers under control of signals like db,dbs,dbr,... (double). This requires embedding conventions for embedding single precision numbers into 64-bit data.
Silvia Melitta Mueller, Wolfgang J. Paul
Chapter 9. Pipelined DLX Machine with Floating Point Core
Abstract
IN THIS chapter, the floating point unit from the previous chapter is integrated into the pipelined DLX machine with precise interrupts constructed in chapter 5. Obviously, the existing design has to be modified in several places, but most of the changes are quite straightforward.
Silvia Melitta Mueller, Wolfgang J. Paul
Backmatter
Metadaten
Titel
Computer Architecture
verfasst von
Silvia Melitta Mueller
Wolfgang J. Paul
Copyright-Jahr
2000
Verlag
Springer Berlin Heidelberg
Electronic ISBN
978-3-662-04267-0
Print ISBN
978-3-642-08691-5
DOI
https://doi.org/10.1007/978-3-662-04267-0