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2005 | Buch

TLM: An Overview and Brief History Kapitel lesen Erstes Kapitel lesen

Transaction Level Modeling with SystemC

TLM Concepts and Applications for Embedded Systems

herausgegeben von: Frank Ghenassia

Verlag: Springer US

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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SUCHEN

Über dieses Buch

Currently employed at STMicroelectronics, Transactional-Level Modeling (TLM) puts forward a novel SoC design methodology beyond RTL with measured improvements of productivity and first time silicon success.

The SystemC consortium has published the official TLM development kit in May 2005 to standardize this modeling technique. The library is flexible enough to model components and systems at many different levels of abstractions: from cycle-accurate to untimed models, and from bit-true behavior to floating-point algorithms. However, careful selection of the abstraction level and associated methodology is crucial to ensure practical gains for design teams.

Transaction-Level Modeling with SystemC presents the formalized abstraction and related methodology defined at STMicroelectronics, and covers all major topics related to the Electronic System-Level (ESL) industry:

- TLM modeling concepts
- Early embedded software development based on SoC virtual prototypes
- Functional verification using reference models
- Architecture analysis with mixed TLM and cycle accurate platforms
- Unifying TLM and RTL with platform automation tools

Complementary to the book, open source code to put this approach into practice is available on several Internet sites as indicated in the first chapter.

Inhaltsverzeichnis

Frontmatter
Chapter 1. TLM: An Overview and Brief History
Abstract
The trend of “the smaller the better” in semiconductor industry pictures a bright future for System-on-Chip (SoC). The full exploitation of new silicon capabilities, however, is limited by the tremendous SoC design complexity to be addressed within very short project schedule. This limiting factor has pushed the need for altering the classic SoC design flow into prominence. A novel SoC design flow starting from a higher abstraction level than RTL, i.e. System-to-RTL design flow, has surfaced as a real need in advanced SoC design teams. After a decade of attempts to define a useful intermediate abstraction between SoC paper specification and synthesizable RTL, the SystemC C++ open-source class library has finally emerged as the right vehicle to explore the adequate level of abstraction. Transaction Level Modeling (TLM), a methodology based upon such abstraction, has proven revolutionary values in bringing software and hardware teams together using the unique reference model; resulting in dramatic reduction of time-to-market and improvement of SoC design quality.
Frank Ghenassia, Alain Clouard
Chapter 2. Transaction Level Modeling
An Abstraction Beyond RTL
Abstract
Transaction level modeling (TLM) is put forward as a promising solution above Register Transfer Level (RTL) in the SoC design flow. This chapter formalizes TLM abstractions to offer untimed and timed models to tackle SoC design activities ranging from early software development to architecture analysis and functional verification. The most rewarding benefit of TLM is the veritable hardware/software co-design founded on a unique reference, culminating in reduced time-to-market and comprehensive cross-team design methodology.
Laurent Maillet-Contoz, Frank Ghenassia
Chapter 3. TLM Modeling Techniques
Based on SystemC
Abstract
The TLM concept and methodology are attainable through an implementation founded on the appropriate system level modeling language. Among the abundant choices of system level languages, we have adopted SystemC as our modeling vector at the transactional level for SoCs. This chapter pulls together our development work to date as a concise illustration of the TLM modeling techniques with a particular focus on SoC communication.
Laurent Maillet-Contoz, Jean-Philippe Strassen
Chapter 4. Embedded Software Development
Through The TLM Approach
Abstract
Early embedded software development, covering coding, testing, integration and validation, is one of the most important targets of TLM platform methodology. This chapter describes mainly the close relationship between the TLM platform and the software running on it. The description illustrates how the software can benefit greatly from the early TLM platform availability. Reciprocally, hardware developers can also benefit from the early feedback on their design when used by the software developers. The TLM platform can therefore be considered as the meeting point between hardware and software development teams.
Eric Paire
Chapter 5. Functional Verification
From The TLM Perspective
Abstract
Functional verification has traditionally focused on providing tools to generate tests and measuring their so-called coverage. The need to provide the correct reference data has had however relatively little attention. This chapter describes how to apply TLM models as executable functional specifications to generate the compulsory reference data required by functional verification environments. We further explain how these models can be used in conjunction with other verification techniques such as hardware emulators, and how formal verification techniques can be applied to TLM models.
Thibaut Bultiaux, Stephane Guenot, Serge Hustin, Alexandre Blampey, Joseph Bulone, Matthieu Moy
Chapter 6. Architecture Analysis and System Debugging
A Transactional Debugging Environment
Abstract
Given the complexity of SoC development in the nanotechnology, it has become critical to fully validate the system performance at the early stage of the SoC design flow. This chapter describes the tools and methods for evaluating the overall SoC interconnect performance, for which the commercial solutions are not yet available. The proposed methodology is based on SystemC simulation using a generic IP Traffic Generator (IPTG) and a powerful monitoring mechanism called SysProbe, which are applicable all through the SoC analysis flow ranging from the transactional to register transfer level (RTL) simulations. Such Traffic Generators model the system IPs and the system traffic dependency with a refinement flow, while real slaves or targets are used to generate the correct latency. The SoC architecture is modeled either at the transactional or RTL level according to the requirements of development costs, simulation speed and precision. SysProbe provides the results of the architectural analysis to SoC architects.
Antoine Perrin, Gregory Poivre
Chapter 7. Design Automation
Integrating TLM in SoC Design Flow
Abstract
Although the TLM development and usage only require a C++ development environment and a SystemC library, design automation is the key to integrating TLM in the SoC design flow for further reaping the design productivity and quality rewards brought by TLM. This chapter explains how TLM has been integrated in the design flow at STMicroelectronics both by extending the SPIRIT XML packaging standard to support TLM and by developing the tools needed to integrate TLM in the flow.
Christophe Amerijckx, Stephane Guenot, Amine Kerkeni, Serge Hustin
Backmatter
Metadaten
Titel
Transaction Level Modeling with SystemC
herausgegeben von
Frank Ghenassia
Copyright-Jahr
2005
Verlag
Springer US
Electronic ISBN
978-0-387-26233-8
Print ISBN
978-0-387-26232-1
DOI
https://doi.org/10.1007/b137175

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