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2012 | Buch

Logic Variables and Events Kapitel lesen Erstes Kapitel lesen

Logic Circuit Design

Selected Methods

verfasst von: Shimon P. Vingron

Verlag: Springer Berlin Heidelberg

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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Über dieses Buch

In three main divisions the book covers combinational circuits, latches, and asynchronous sequential circuits. Combinational circuits have no memorising ability, while sequential circuits have such an ability to various degrees. Latches are the simplest sequential circuits, ones with the shortest memory. The presentation is decidedly non-standard.

The design of combinational circuits is discussed in an orthodox manner using normal forms and in an unorthodox manner using set-theoretical evaluation formulas relying heavily on Karnaugh maps. The latter approach allows for a new design technique called composition.

Latches are covered very extensively. Their memory functions are expressed mathematically in a time-independent manner allowing the use of (normal, non-temporal) Boolean logic in their calculation. The theory of latches is then used as the basis for calculating asynchronous circuits.

Asynchronous circuits are specified in a tree-representation, each internal node of the tree representing an internal latch of the circuit, the latches specified by the tree itself. The tree specification allows solutions of formidable problems such as algorithmic state assignment, finding equivalent states non-recursively, and verifying asynchronous circuits.

Inhaltsverzeichnis

Frontmatter

Combinational Circuits

Frontmatter
Chapter 1. Logic Variables and Events
Abstract
Switching circuits process binary input signals logically, the result itself being a binary output signal. The logical operations used in processing the input signals require the binary signals to be transformed into logic variables. Giving substance to the previous two sentences is the subject of this chapter.
Shimon P. Vingron
Chapter 2. Switching Devices
Abstract
Logic gates, as introduced in the previous chapter, represent the connectives used in logic formulas. Assume you have drawn a circuit diagram using logic gates, and you now want to build the circuit using switching devices of a given technology (pneumatic, electric, or electronic). To be able to do so you need to know how to translate each logic symbol into a symbol or a collection of symbols of the technology you intend to employ. This chapter is restricted to discussing symbols used forpneumatic valves,electric relays, andCMOS transistors, and to showing how they correspond to logic gates.
Shimon P. Vingron
Chapter 3. Elementary Logic Functions
Abstract
Elementary logic functions are the building blocks of all logic functions however complicated they may be, and are thus of prime importance. In the following pages we discuss all elementary logic functions and how they interact. Much of this material, such as the summaries of theorems, is only intended as reference to be at hand when needed (e.g., in calculations, or for theoretical considerations).
Shimon P. Vingron
Chapter 4. Normal Forms
Abstract
Normal forms are the classical logic formulas by which to calculate logic circuits. The output connective of a normal form must be associative restricting the number of normal forms to four, i.e., to formulas whose (multi-input) output connective is either AND, OR, XOR or EQU.
Shimon P. Vingron
Chapter 5. Karnaugh Maps
Abstract
In the previous chapter we used an events graph to specify a combinational circuit, and normal forms to calculate its logical design, here touching on the practical necessity to minimise (or simplify) the formulas obtained when employing canonical normal forms. In contrast to this somewhat formal approach, Karnaugh (1953), building on Veitch (1952), presented a graphic specification method with a marked theoretical potential by which to stimulate deeper insight and the development of new concepts.
Shimon P. Vingron
Chapter 6. Adjacency and Consensus
Abstract
This chapter is a precursor to algebraic minimisation taken up in the next chapter. The operators and methods developed here are inspired by the visual methods used in evaluating K–maps. It is helpful to have a clear intuitive grasp of the concepts we want to use formally, so, in Sect. 6.1 we introduce the two prime concepts, adjacency and consensus, in a visual and informal way. Only in the next two sections do we define these concepts formally. The last section, Sect. 6.4, is devoted to the question, when one K-set is a (proper) subset of another.
Shimon P. Vingron
Chapter 7. Algebraic Minimisation
Abstract
Minimising relatively small switching functions (of no more than, say, six input variables) can be done quite efficiently by K-map. Larger problems should be solved by computer. To be able to write computer programs for minimisation, we need to (a) develop an algorithm by which to find a full cover, and (b) a further algorithm by which to select a minimal cover from the full cover.
Shimon P. Vingron
Chapter 8. Design by Composition
Abstract
The normal forms discussed in Chap. 4 allow us to design combinational circuits using only basic elementary connectives: The canonical normal forms employ AND, OR, and NOT, while the Zhegalkin normal forms realise circuits with XOR and AND or, respectively, with EQU and OR. Taking circuit design to a higher level, we would want to use the normal forms to design small circuit modules if only we had a procedure that would allow us to put these modules together so as to realise a specified problem. Such a process is referred to as composing a circuit (using previously developed and usually well-tested modules). In the simplest case, these modules can themselves be elementary connectives, e.g., NAND or NOR. But the power of a composition procedure lies in its ability to cope with more complicated modules. The composition procedure presented here is taken from Vingron (2004). The converse to composition is decomposition, a procedure developed by Ashenhurst’s (1959) in which he showed how to split a switching function into two smaller functions, each, hopefully, being easier to realise.
Shimon P. Vingron

Latches

Frontmatter
Chapter 9. Basic Theory of Latches
Abstract
To be able to develop an abstract concept of a latch, we need something from which to abstract. Section 9.1 introduces us to a number of devices and a circuit that intuitively have in common a property we call memorisation. Devices with this property are referred to as latches.
Shimon P. Vingron
Chapter 10. Designing Feedback Latches
Abstract
The memory evaluation-formulas of the previous chapter are the backbone to designing feedback latches (such as the relay circuit of Fig. 9.1b). Yet, feedback can only be realised if we can show that the prior output Y (λ − 1) may always (i.e., for all input events) be chosen to equal the present output Y (λ)—for then and only then can we connect the two leads, thus realising feedback.
Shimon P. Vingron
Chapter 11. Elementary Latches
Abstract
This chapter presents an overview of the elementary latches, first classifying them, and then developing a system of latch symbols. The few latch symbols standardised in IEC 117–15 or IEEE 91–1984 simply don’t cover the problem.
Shimon P. Vingron
Chapter 12. Latch Composition
Abstract
Methodologically, the composition of latches is an extension to the composition of combinational circuits, discussed in Chap.8, and is thus based on the catenation of functions. Latch composition allows us to realise a given (or specified) latch f by employing a chosen latch h as the hinge function, and developing for these the generic function g as a combinational circuit, a circuit called the pre-logic ofh. The composition problem of latches boils down to finding, or developing, the combinational pre-logic g which satisfies the catenation hg = f for the given memory functions f and h. The theory of latch composition is put forth quite extensively in the first section.
Shimon P. Vingron

Asynchronous Circuits

Frontmatter
Chapter 13. Word-Recognition Tree
Abstract
A sequential circuit reacts to sequences of input events. A sequence of input events is called an input word. A sequential circuit is specified by the shortest and the least number of input words that determine the circuit’s behaviour. As both these properties (the length of input words, and the number of input words) are finite, the number of memory elements needed to realise a sequential circuit is also finite. A sequential circuit can be specified by a tree that allows us to mark the effect input words have on the circuit’s output. Such a tree allows us to pinpoint or recognise all the words needed to define the circuit—we thus call these trees word-recognition trees; they were devised by Vingron (1982). In this chapter we introduce the word-recognition trees by example, at the same time showing that they enable a direct derivation of the circuit.
Shimon P. Vingron
Chapter 14. Huffman’s Flow Table
Abstract
The word-recognition tree, put forth in the previous chapter, has two pronounced drawbacks: it does not readily lend itself to formulating the behaviour of more complicated sequential problems intuitively, and it is not helpful in analysing the behaviour of a given circuit. Both these problems are addressed by the so-called flow table conceived and introduced by Huffman (1954). This chapter presents the flow table as a program which governs the behaviour of an abstract automaton called a sequential automaton in this text. The sequential automaton, together with a flow table, produces an events graph: the sequence of input events of the events graph being the sequence of inputs to the automaton, the sequence of associated output values of the events graph being the successive and associated outputs of the automaton.
Shimon P. Vingron
Chapter 15. State-Encoding by Iterative Catenation
Abstract
At first sight a flow table gives hardly a hint as how to design a binary circuit. But, as this chapter shows, there is a strait forward method to develop the associated word-recognition tree, this, subsequently, allowing us to calculate and design a circuit as discussed in Chap. 13. The word-recognition tree is obtained, firstly, by a binary encoding of the states of the flow table, and, secondly, by an appropriate interpretation of the state encoding
Shimon P. Vingron
Chapter 16. Circuit Analysis
Abstract
In this chapter we look into the two main aspects of circuit analysis. Firstly, how can one find and describe the external behaviour, the so-called input–output behaviour, of a circuit? An answer is more often necessary than meets the eye, as it is still quite common to develop circuits intuitively, thus not being able to guarantee certain subtleties in their IO-behaviour. But you can also view this aspect as that of reverse engineering, or as a first step in circuit optimisation. Depending on which of the above points you want to emphasize, you might formulate your answer as a flow table, an events graph, or a word-recognition tree. Secondly, and this is the aspect of internal behaviour, we want to look into how the internal latches work together to avoid malfunctioning of the circuit. This malfunctioning can, as we will see, cause transient erroneous output signals in the event of non-critical races between internal latches, or permanently wrong output signals in the event of what we call critical races between internal latches.
Shimon P. Vingron
Chapter 17. State Reduction
Abstract
State reduction refers to finding some or all mutually equivalent states of a flow table, and dropping (i.e., merging) from each set of equivalent states all but one state. Equivalent states of a flow table are those rows in the flow table’s transition table that are mutually identical. All merged variants of a flow table have one and the same word-recognition tree which is why we call the merged transition tables equivalent. The rows that can be dropped are referred to as redundant. This concept of state reduction is as simple as it is novel, and is presented in place of the rather unwieldy, standard, recursive procedure.
Shimon P. Vingron
Chapter 18. Verifying a Logic Design
Abstract
The problem considered in this chapter is this: Having designed an asynchronous circuit according to a given word-recognition tree, or flow table, we next want to verify our logic design by developing a minimal length events graph with which to completely test the circuit’s input–output behaviour. In the literature, this is usually referred to as functional testing. In general, the problem is seen as unsolvable. Mead and Conway (1980) put it this way: ‘Complete functional testing of complex systems with internal sequencing is not possible in general, and most integrated system chips manufactured, even at 1978 levels of complexity, are not economically testable for even a small fraction of their possible internal states.’
Shimon P. Vingron
Backmatter
Metadaten
Titel
Logic Circuit Design
verfasst von
Shimon P. Vingron
Copyright-Jahr
2012
Verlag
Springer Berlin Heidelberg
Electronic ISBN
978-3-642-27657-6
Print ISBN
978-3-642-27656-9
DOI
https://doi.org/10.1007/978-3-642-27657-6

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