Anzeige
Erschienen in:
2005 | OriginalPaper | Buchkapitel
Minimizing Power in Hardware/Software Partitioning
verfasst von : Jigang Wu, Thambipillai Srikanthan, Chengbin Yan
Erschienen in: Advances in Computer Systems Architecture
Verlag: Springer Berlin Heidelberg
Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.
Wählen Sie Textabschnitte aus um mit Künstlicher Intelligenz passenden Patente zu finden. powered by
Markieren Sie Textabschnitte, um KI-gestützt weitere passende Inhalte zu finden. powered by
Power efficiency is one of the major considerations in the current hardware/software co-designs. This paper models hardware/ software partitioning as an optimization problem with the objective of minimizing power consumption. An efficient heuristic algorithm running in
O
(
n
log
n
) is proposed by extending the idea of solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution in
$O(n.\mathcal{A}.\mathcal{E})$
for
n
code fragments under the constraints: hardware area
$\mathcal{A}$
and execution time
$\mathcal{E}$
. Computational results show that the approximate solution produced by the proposed heuristic algorithm is nearly optimal in comparison to the optimal solution produced by the proposed exact algorithm.