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Model Generation in Electronic Design

herausgegeben von: Jean-Michel Bergé, Oz Levia, Jacques Rouillard

Verlag: Springer US

Buchreihe : Current Issues in Electronic Modeling

Enthalten in: Professional Book Archive

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Über dieses Buch

Model Generation in Electronic Design covers a wide range of model applications and research. The book begins by describing a model generator to create component models. It goes on to discuss ASIC design and ASIC library generation. This section includes chapters on the requirements for developing and ASIC library, a case study in which VITAL is used to create such a library, and the analysis and description of the accuracy required in modeling interconnections in ASIC design.
Other chapters describe the development of thermal models for electronic devices, the development of a set of model packages for VHDL floating point operations, a techniques for model validation and verification, and a tool for model encryption.
Model Generation in Electronic Design is an essential update for users, vendors, model producers, technical managers, designers and researchers working in electronic design.

Inhaltsverzeichnis

Frontmatter

1. A Flexible Generator of Component Models

Abstract

We present in this paper an automatic tool generating component models built according to a varied choice of modeling rules as well as specification formats. It can substantially aid to build libraries of models. The core of the generator is based on an intermediate format, common for all these input formats and for all possible modeling rules. Around it, a designer may define and/or easily implement as many specification formats and sets of modeling techniques as needed. The generator is described in detail, tested for VHDL models of standard cells, and compared to a ‘classical ’ generator of component models.

Marcus Blüml, Frédérique Bouchard, Adam Pawlak

2. What Makes an ASIC Library Sign-Off?

Abstract

Sign-off quality ASIC libraries must be sufficiently accurate to ensure that test programs created from simulations using the library will match the behavior of the part on the tester. The libraries should not be excessively conservative, and should model cell behavior in an appropriate manner to take advantage of the capabilities of the latest design tools offered by EDA vendors. Automating the creation and verification of models can reduce the time and effort required to support high-quality sign-off libraries.

Greg Haynes

3. A Case History in Building Vital-Compliant Models

Abstract

This paper presents the evolution of an emerging VHDL modeling methodology, called VITAL, which aims at writing accurate and portable VHDL models for ASIC gate libraries. We also provide here a comparison of VITAL performances to classical simulations.

Przemyslaw Bakowski, Frédérique Bouchard, Jean-Paul Caïsso, Frédéric Igier

4. Modeling Multiple Driver Net Delay in Simulation

Abstract

With advances in IC technology and performance have come requirements for additional and more detailed timing analyses. Historically, the effect on timing of the design interconnect (particularly transmission delay) has not represented a significant factor at the IC level. However, as technology pushes below the 1-micron barrier, it is expected that these interconnect factors will no longer be ignored. The timing delay analysis (simulation) required by many ASIC foundries for sign-off will likely require the inclusion of interconnect (wire) delays.

The inclusion of wire delays in simulation is non-trivial from the modeler’s perspective. There is often no defined language construct for the specification of wire delay. The wire delay behavior must be explicitly coded, either as a part of the behavior of leaf components or using special ‘wire’ components. It is simpler (at the netlist level) if the wire delay is included in the leaf (cell) models. However, this approach is generally limited to single-driver interconnects. This paper reviews the requirements associated with modeling wire delay and presents a general-purpose wire delay component model that can support both single- and multi-driver wire delays.

Ray Ryan

5. DELPHI: The Development of Libraries of Physical Models of Electronic Components for an Integrated Design Environment

Abstract

The accurate prediction of operating temperatures of critical electronic parts at the component-, board- and system-level is seriously hampered by the lack of reliable, standardised input data. This paper describes a recently-started 3-year European collaborative project, named DELPHI, whose goal is to solve this problem. Some preliminary results are reported on the development of compact thermal models for mono-chip packages. It is the authors’ contention that a future redefinition of the standards is to be expected, is necessary and should include protocols for thermal models in addition to ones for measurements.

In the first section of this paper a review is provided of the methods in use for the thermal characterization of component packages with especial emphasis on mono-chip packages. The second section describes the DELPHI project including a discussion of experimental requirements and the issue of international standardization. The third section explains the results of preliminary investigations on an idealized mono-chip package. The fourth section gives results for a real package, namely a 208-lead Plastic Quad Flat Pack. The final section provides conclusions and directions for future research. The paper finishes with acknowledgements, references and an appendix which contains results for the 208-lead PQFP modelling.

Although DELPHI is concerned with a variety of electronic parts including mono-chip packages, heat sinks, thermal interface materials, etc, this paper focuses on the thermal characterization of mono-chip packages.

Harvey I Rosten, Clemens J M Lasance

6. VHDL Floating Point Operations

Abstract

In this paper, we present a set of portable floating point VHDL functions. These functions provide the VHDL programmer with absolute portability and very precise control over floating point operations. A single VHDL type is used to represent single, double, and extended precision floating point numbers. The VHDL package includes functions to perform relational, arithmetic, and trigonometric floating point operations on all three precisions. This package was designed to be easily maintained and upgraded to include new floating point precisions or operations. We also describe a method for verifying the results from the VHDL package of floating point operations.

George S. Powley Jr., Joanne E. DeGroat

7. Symbolic Model Checking with Past and Future Temporal Modalities: Fundamentals and Algorithms

Abstract

Model checking is gaining importance in verifying the partial specifications of complex synchronous systems modelled by means of a finite state machine. In this paper, we present the principles and a tool for checking their properties in a temporal logic that allows both past and future oriented modalities. After a revision of the basic concepts of the finite state machine model, and of its representation using binary decision diagrams, we present several algorithms to traverse the set of states symbolically. We then extend CTL with past oriented modalities and give properties of this extended temporal logic(TL). We give algorithms to verify TL formulas by symbolic model checking. A prototype symbolic model checker for TL, taking as input synchronous circuits written in a VHDL subset, has been implemented.

David Déharbe, Dominique Borrione

8. KRYPTON: Portable, Non-Reversible Encryption for VHDL

Abstract

In this paper, we present KRYPTON, an encryption tool for models written in VHDL. KRYPTON differs from standard, object code-based approaches in two major areas. First of all, KRYPTON generates a VHDL source code — meaning that it is possible to execute the encrypted code on all standard VHDL platforms. Secondly, the transformations applied render the original code non-recoverable. Transformations are divided into two sets, encryption-oriented and synthesis-oriented. The first set aims to eliminate the intelligibility of the code. The second set tries to remove the synthesizabilty of the code. KRYPTON has been successfully tested on models containing over 100 VHDL units.

Kevin O’Brien, Serge Maginot

Backmatter

Titel: Model Generation in Electronic Design
herausgegeben von: Jean-Michel Bergé
Oz Levia
Jacques Rouillard
Verlag: Springer US
Electronic ISBN: 978-1-4615-2335-2
Print ISBN: 978-1-4613-5989-0
DOI: https://doi.org/10.1007/978-1-4615-2335-2

Springer Professional

Über dieses Buch

Inhaltsverzeichnis

Frontmatter

1. A Flexible Generator of Component Models

2. What Makes an ASIC Library Sign-Off?

3. A Case History in Building Vital-Compliant Models

4. Modeling Multiple Driver Net Delay in Simulation

5. DELPHI: The Development of Libraries of Physical Models of Electronic Components for an Integrated Design Environment

6. VHDL Floating Point Operations

7. Symbolic Model Checking with Past and Future Temporal Modalities: Fundamentals and Algorithms

8. KRYPTON: Portable, Non-Reversible Encryption for VHDL

Backmatter