Modeling and Simulation of Mixed Analog-Digital Systems

Integrated circuit technology is perhaps one of the fastest growing technology sectors, with rapid progress being made in the design and fabrication processes. The design of more complex and increasingly dense designs continues at a frantic pace. Rapid scaling of device sizes now enables complete systems to be integrated on chip. The newer generations of integrated circuits are no longer purely analog or digital but include a combination of different functionalities. Mixed signal system design that largely combine analog and digital sections has also evolved into a field of its own to keep pace with this technology trend. We devote this special issue to report on the leading-edge enabling developments in the modeling and simulation area, necessary to support and fuel the mixed-signal design trend. In this issue we have collected an excellent representative set of papers that covers different aspects of this area.

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular, signal crosstalk through the common chip substrate has become increasingly problematic. This paper demonstrates a methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. First, a triangular discretization method is employed to generate RC equivalent-circuit substrate models which are far less complex than those formulated by conventional techniques. The networks are then accurately approximated for subsequent analysis by an efficient reduction algorithm which uses a well-conditioned Lanczos moment-matching process. Through congruence transformations, the network admittance matrices are transformed to reduced equivalents which are easily post-processed to derive passive, SPICE-compatible netlist representations of the reduced models. The pure-RC properties of the extracted substrate networks are fully exploited to formulate an efficient overall algorithm. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.

Phase-locked Loops(PLLs) are a class of feedback systems with wide range of applications. A PLL in its entirety can be viewed as a closed-loop servosystem, comprised of three major functional subsystems; 1) Phase detectors, 2) Loop filters and 3) Voltage/Current controlled oscillators. The overall characteristics of the phase-locked loop are dependent on the realization of individual subsystems which have mixed analog-digital implementations. In simulating a PLL, one has to deal with the mixed-signal nature of most implementations, as well as the problem of simulating the PLL over a large number of signal cycles. Long simulation run times plague the simulation of a PLL using a conventional simulator, sometimes making such simulation impractical. In the methodology described in this paper, these drawbacks are overcome by the use of behavioral models and a mixed-signal simulation platform. This paper presents a general mixed-mode behavioral simulation methodology and the derivation of behavioral simulation models for various kinds of PLLs. The top-down and bottom-up modeling paradigms are illustrated through the use of examples of actual PLL designs. The simulation models are generated for the AT&T Bell Laboratories mixed analog-digital simulator, ATTSLM.

In this paper we will demonstrate that most digital, analog as well as behavioral components can be described using piecewise linear approximations of their real behavior. This leads to several advantages from the viewpoint of simulation. We will also give a method to store the resulting linear segments in a compact way, in order to avoid storage problems.

The analog cellular neural network (CNN) model is a powerful parallel processing paradigm in solving many scientific and engineering problems. The network consists of densely-connected analog computing cells. Various applications can be accomplished by changing the local interconnection strengths, which are also called coefficient templates. The behavioral simulator could help designers not only gain insight on the system operations, but also optimize the hardware-software co-design characteristics. An unique feature of this simulator is the hardware annealing capability which provides an efficient method of finding globally optimal solutions. This paper first gives an overview of the cellular network paradigm, and then discusses the nonlinear integration techniques and related partition issues, previous work on the simulator and our own simulation environment. Selective simulation results are also presented at the end.

This paper presents a hierarchical fault modeling approach for catastrophic as well as out-of-specification (parametric) faults in analog circuits. These include both, ac and dc faults in passive as well as active components. The fault models are based on functional error characterization. Case studies based on CMOS and nMOS operational amplifiers are discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level. Application of these fault models in an efficient fault simulator for analog circuits is also described.

A mixed analog/digital ASIC from a real satellite application (a radiation detector front-end) has been designed, simulated and processed according to a hierarchical top-down design methodology. CAD tools (commercial and academic) have been used as much as possible. The top-down methodology is discussed and illustrated by going through the different steps of the ASIC design. At each level the different choices and tradeoffs are briefly discussed and practical difficulties of top-down design are pointed out. One of the most important problems in top-down mixed-signal ASIC design—modeling and verification—is highlighted and discussed in detail.

This paper describes the modeling for the analysis of electro-optical devices using a conventional electrical simulator. The proposed approach is intended for the analysis of optical sensor systems, which have optical and electronic devices integrated on the same silicon chip. Models have been developed using a hardware description language for the following devices: the LED, the photodiode and the absorbing medium. Suitable approximations allow the models to be accurate with a limited number of parameters while the computation time is kept sufficiently short. Simulation results show good agreement between numerical analysis and experimental data previously reported in the literature.