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Erschienen in:
2012 | OriginalPaper | Buchkapitel
Operand Folding Hardware Multipliers
verfasst von : Byungchun Chung, Sandra Marcello, Amir-Pasha Mirbaha, David Naccache, Karim Sabeg
Erschienen in: Cryptography and Security: From Theory to Applications
Verlag: Springer Berlin Heidelberg
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This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the partitions. The resulting design turns-out to be both compact and fast.
When the operands’ bit-length
m
is 1024, the new algorithm requires only 0.194
m
+ 56 additions (on average), this is about half the number of additions required by the classical accumulate-and-add multiplication algorithm (
$\frac{m}2$
).