2016 | OriginalPaper | Buchkapitel
Optimization of Adder Graphs with Ternary (3-Input) Adders
verfasst von : Martin Kumm
Erschienen in: Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays
Verlag: Springer Fachmedien Wiesbaden
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Modern FPGAs provide the possibility to realize ternary adders, i.e., adders with three inputs, by using the same hardware resources as for common two-input adders. As shown in Section 2.5.3, the LUTs in RCAs are underutilized or even not used. These LUTs can often not be used to implement other logic functions due to routing constraints.