Photonic Network-on-Chip Design

Over the past four decades the progress of computing systems was largely dominated by the underlying acceleration in microprocessor performance and extraordinary advances in semiconductor technology. Improved fabrication methods and increasing die sizes were manifested in Moore’s law, predicting in 1965 that the number of transistors integrated on a single die will be roughly doubled every two years [1]. Along with additional advances in circuit design techniques and processor microarchitectures, these improvements led to rapidly increasing clock speeds and to the extremely-high performance presented by CMOS-based microprocessors.

This chapter describes the most important characteristics and performance metrics of chip-scale communications. Figure 2.1 illustrates the general structure of all optical communication channels, which comprises of the communicating nodes and the optical link itself. The optical link consists of three functional elements: (1) generation, (2) routing, and (3) reception. Generation happens near a source node and involves the creation of a waveform in the optical domain for transporting useful information. Routing is for controlling the movement of optical data so that the useful information can travel from the source node to the destination node. Lastly, reception enables the optical link to translate the useful information back into the electrical domain to be used by the computing resource at the destination node. These three components (generation, routing, and reception) encompass everything needed for optical communications.

Systems harnessing silicon photonic technology have the potential to vastly improve the performance of interconnects and computing systems. This chapter provides insight into this emerging technology, and summarizes several critical empirical results. Key conclusions that can be drawn from these demonstrations are highlighted, followed by discussions on relevant performance metrics and their corresponding challenges.

As discussed in the previous chapter, the progress in silicon photonics research has enabled the physical demonstration of all the devices that are necessary to build extremely high-bandwidth density and energy-efficient links for on-chip and off-chip communications. Photonic network design, however, requires a major paradigm shift from traditional network design due to the fundamental differences in how electronics and photonics operate. Consequently, new modeling and analysis methods must be employed to realize a chip-scale photonic interconnection network. This chapter describes a methodology and a supporting computer-aided design (CAD) environment to model the basic photonic devices, to combine them to realize photonic network architectures, and to analyze the physical-layer and system-level performance properties of these networks.

A photonic network design encompasses a wide range of details that must be considered carefully. Design details include material system, layout of components, and network arbitration mechanisms. Each detail involves several metrics including performance requirements, power constraints, scalability, and cost. Designing a photonic network which is both feasible and cost-effective is a multi-dimensional design-space problem in which all the parts are tightly coupled.

Wavelength-routed networks use individual wavelengths which can be statically or dynamically allocated to source-destination pairs using combinations of modulators, filters, and waveguides. Wavelength-routed networks use wavelength selectivity in order to route data through the network, in contrast to circuit-switched networks which utilize wavelength selectivity for bandwidth aggregation. The wavelength arbitration technique limits the point-to-point bandwidth to a subset of the total number of wavelengths available in the system. This chapter considers architectures where each point-to-point link is composed of a single wavelength channel (unless specified) for simplicity of discussion. This assumption is true of most wavelength-routed networks that have been proposed in literature. These architectures typically exhibit lower latencies than circuit-switched architectures since they do not require the path-setup protocol. Fundamentally, the latency of wavelength-routed networks is only limited by the speed of light and the time required to perform CDR. This chapter describes some of the fundamental building blocks of wavelength-routed architectures and explores some examples of architectures that have been proposed.

Circuit-switching is a natural use of the photonic transmission medium because it is a simple solution that abstracts many of the physical layer implementation details in network design. However, it can suffer from severe network congestion and starvation when long-lived communication patterns occur. This chapter explores some architectural variations on circuit-switched networks to alleviate some of these issues

Among the technologies that are emerging in the age of end-of-scaling CMOS, silicon photonics is perhaps the most promising to enable a smooth transition toward a new generation of post-CMOS computing systems. During the past decade a series of major breakthroughs in silicon photonic devices have demonstrated that all the components that are necessary to build chip-scale photonic interconnect components (e.g. modulators, filters, switches, detectors) can be fabricated using common CMOS processes. This key property of silicon photonics could allow a gradual integration of optical communication into CMOS integrated circuits. The photonics role can be increasingly expanded until it becomes central for the systems built with those so-called More-than-Moore technologies. Critically, during this transition silicon photonics could enable continued scaling of performance for a variety of applications because the unique properties of a chip-scale photonic network are not limited to the cross-chip communication distances. Instead, on-chip, board-scale, and cluster-scale distances are all equivalent in terms of optical communication performance. This is a fundamental difference with electronic communications, which must adhere to stricter bandwidth-distance product limitations.