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Erschienen in:
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2013 | OriginalPaper | Buchkapitel

1. Regular Versus Irregular TSV Placement for 3D IC

verfasst von : Sung Kyu Lim

Erschienen in: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Verlag: Springer New York

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Abstract

Through-silicon via (TSV) is the enabling technology for fine-grained integration of multiple dies into a single 3D stack. However, TSVs occupy significant silicon area due to their sheer size, which has a great effect on the power and performance of 3D ICs. Whereas well-managed TSVs alleviate routing congestion, reduce wirelength, and improve performance, excessive or ill-managed TSVs not only increase the die area but also degrade performance and power. In this chapter, we study the impact of TSVs on the quality of 3D IC layouts. We first study two design schemes, namely TSV co-placement (irregular TSV placement) and TSV site (regular TSV placement), for the design of 3D ICs. In addition, we develop a force-directed 3D gate-level placement algorithm to find optimal locations of TSVs and gates. One key problem to solve in regular TSV placement is how to assign 3D nets to pre-placed TSVs. To solve this problem effectively, we study two TSV assignment algorithms, compare them with other TSV assignment algorithms, and analyze the impact of the quality of TSV assignment algorithms on 3D ICs. Experimental results show that the wirelength of 3D ICs is shorter than that of 2D ICs by up to 25 %. We also compare timing and power of 2D and 3D ICs.
The materials presented in this chapter are based on [19].

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Nächstes Kapitel Steiner Routing for 3D IC
Fußnoten
1
We use diameter and width for cylindrical-shaped TSVs and square-shaped TSVs, respectively.
 
2
The area overhead caused by a TSV is due to the TSV, liner around the TSV, and keep-out zone. In our work, A TSV of a 1 ×TSV is 6.1009 μm2.
 
3
If we want to apply our design methodology to via-last type TSVs, we need additional steps. For the TSV co-placement flow, we need to avoid overlaps between two TSVs in adjacent dies. This can be resolved by applying another force between two TSVs in adjacent dies or by legalizing TSV locations after global placement. For the TSV-site flow, we can avoid overlaps between two TSVs in adjacent dies by using different TSV array size. If re-distribution layers exist, however, our design methodology can be directly applied to via-last type TSVs.
 
4
When the number of dies increases, if we ignore TSV area, the footprint area monotonically decreases. However, the number of TSVs has a great effect on the footprint area. If too many TSVs are used at a particular partitioning, the footprint area at that die count could increase.
 
5
The TSV capacitance used in [21] is 37 fF for a square-shaped TSV whose width and height are 5 and 50 μm, respectively. In our case, TSV width is 1.50 μm and TSV height is 20 μm, so we actually obtain 4.43 fF for our TSV capacitance by linear scaling because TSV capacitance is almost linearly proportional to TSV width and TSV height [28].
 
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Metadaten
Titel
Regular Versus Irregular TSV Placement for 3D IC
verfasst von
Sung Kyu Lim
Copyright-Jahr
2013
Verlag
Springer New York
Buch
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Print ISBN: 978-1-4419-9541-4

Electronic ISBN: 978-1-4419-9542-1

Copyright-Jahr: 2013

DOI
https://doi.org/10.1007/978-1-4419-9542-1_1

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