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Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2017 | OriginalPaper | Buchkapitel

3. Sample and Hold

verfasst von : Marcel Pelgrom

Erschienen in: Analog-to-Digital Conversion

Verlag: Springer International Publishing

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Abstract

The sample-and-hold circuit or track-and-hold circuit performs the sampling operation. These circuits have to operate at the highest signal levels and speeds, which makes their design a challenge. The chapter discusses first the specific metrics for these circuits, such as pedestal step, droop time, and hold-mode feed-through. The different elements: switch, capacitor, and buffer are discussed. Some architectures and often applied implementation schemes are shown. The trade-off between noise and distortion requires a careful balance to achieve the optimum performance.

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Vorheriges Kapitel Sampling
Nächstes Kapitel Quantization
Fußnoten
1
For convenience reasons the switch is assumed to be implemented as an NMOS transistor, unless otherwise stated. Conduction takes place with a positive gate voltage.
 
2
A relation seems likely with the tales on Baron von Mŭnchhausen, who pulled himself up by his bootstraps, and “booting” of computers.
 
3
The word “source” is used for the device terminal with the arrow in the schematic, irrespective of the voltage.
 
4
The so-called noise-excess factor is disputed, although some correction for the shape of the inversion layer may be applicable.
 
5
Rule of thumb means here that this is a good level to start the discussion, various topologies give different results.
 
6
The four-diode circuit is widely used for rectifying ac-signals under the name Grätz-bridge.
 
7
See also [46] for an elementary discussion on distortion in analog circuits.
 
8
A bipolar circuit is simple to analyze, of course the same holds for an MOS circuit.
 
9
Contributions from higher-order terms are not included.
 
Literatur
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Keramat A, Tao Z (2000) A capacitor mismatch and gain insensitive 1.5-bit/stage pipelined A/D converter. In: Proceedings of the 43rd IEEE midwest symposium on circuits and systems, pp 48–51
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Gregoire BR, Moon U (2008) An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain. IEEE J Solid-State Circuits 43:2620–2630CrossRef
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Wakimoto T, Akazawa Y (1993) Circuits to reduce distortion in the diode-bridge track-and-hold. IEEE J Solid-State Circuits 28:384–387CrossRef
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Vorenkamp P, Verdaasdonk JPM (1992) Fully bipolar, 120-MS/s 10-b track-and-hold circuit. IEEE J Solid-State Circuits 27:988–992CrossRef
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Sansen W (1999) Distortion in elementary transistor circuits. IEEE Trans Circuits Syst II 46:315–325 4. Quantization
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Liu C-C, Chnag S-J, Huang G-Y, Lin Y-Z (2010) A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid-State Circuits 45:731–740CrossRef
Metadaten
Titel
Sample and Hold
verfasst von
Marcel Pelgrom
Copyright-Jahr
2017
Buch
Analog-to-Digital Conversion

Print ISBN: 978-3-319-44970-8

Electronic ISBN: 978-3-319-44971-5

Copyright-Jahr: 2017

DOI
https://doi.org/10.1007/978-3-319-44971-5_3

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