System Reduction for Nanoscale IC Design

herausgegeben von: Peter Benner

Verlag: Springer International Publishing

Buchreihe : Mathematics in Industry

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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Über dieses Buch

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle.

The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Model Order Reduction of Integrated Circuits in Electrical Networks

Abstract

We consider integrated circuits with semiconductors modeled by modified nodal analysis and drift-diffusion equations. The drift-diffusion equations are discretized in space using mixed finite element method. This discretization yields a high-dimensional differential-algebraic equation. Balancing-related model reduction is used to reduce the dimension of the decoupled linear network equations, while the semidiscretized semiconductor models are reduced using proper orthogonal decomposition. We among other things show that this approach delivers reduced-order models which depend on the location of the semiconductor in the network. Since the computational complexity of the reduced-order models through the nonlinearity of the drift-diffusion equations still depend on the number of variables of the full model, we apply the discrete empirical interpolation method to further reduce the computational complexity. We provide numerical comparisons which demonstrate the performance of the presented model reduction approach. We compare reduced and fine models and give numerical results for a basic network with one diode. Furthermore we discuss residual based sampling to construct POD models which are valid over certain parameter ranges.

Michael Hinze, Martin Kunkel, Ulrich Matthes, Morten Vierling

Chapter 2. Element-Based Model Reduction in Circuit Simulation

Abstract

In this paper, we consider model reduction of linear and nonlinear differential-algebraic equations arising in circuit simulation. Circuit equations obtained using modified nodal or loop analysis have a ;special structure that can be exploited to construct efficient model reduction algorithms. For linear systems, we review passivity-preserving balanced truncation model reduction methods that are based on solving projected Lur’e or Lyapunov matrix equations. Furthermore, a ;topology-based index-preserving procedure for extracting large linear subnetworks from nonlinear circuits is given. Finally, we describe a ;new MATLAB Toolbox PABTEC for model reduction of circuit equations and present some results of numerical experiments.

Andreas Steinbrecher, Tatjana Stykel

Chapter 3. Reduced Representation of Power Grid Models

Abstract

We discuss the reduction of large-scale circuit equations with many terminals. Usual model order reduction (MOR) methods assume a small number of inputs and outputs. This is no longer the case, e.g., for the power supply network for the functional circuit elements on a chip. Here, the order of inputs/outputs, or terminals, is often of the same order as the number of equations. In order to apply classical MOR techniques to these power grids, it is therefore mandatory to first perform a terminal reduction. In this survey, we discuss several techniques suggested for this task, and develop an efficient numerical implementation of the extended SVD MOR approach for large-scale problems. For the latter, we suggest to use a truncated SVD computed either by the implicitly restarted Arnoldi method or the Jacobi-Davidson algorithm. We analyze this approach regarding stability, passivity, and reciprocity preservation, derive error bounds, and discuss issues arising in the numerical implementation of this method.

Peter Benner, André Schneider

Chapter 4. Coupling of Numeric/Symbolic Reduction Methods for Generating Parametrized Models of Nanoelectronic Systems

Abstract

This chapter presents new strategies for the analysis and model order reduction of systems of ever-growing size and complexity by exploiting the hierarchical structure of analog electronical circuits. Thereby, the entire circuit is considered as a system of interconnected subcircuits. Given a prescribed error-bound for the reduction process, a newly developed algorithm tries to achieve a maximal reduction degree for the overall system by choosing the reduction degrees of the subcircuits in a convenient way. The individual subsystem reductions with respect to their prescribed error-bound are then performed using different reduction techniques. Combining the reduced subsystems a reduced model of the overall system results. Finally, the usability of the new techniques is demonstrated on two circuit examples typically used in industrial applications.

Oliver Schmidt, Matthias Hauser, Patrick Lang

Chapter 5. Low-Rank Cholesky Factor Krylov Subspace Methods for Generalized Projected Lyapunov Equations

Abstract

Large-scale descriptor systems arising from circuit simulation often require model reduction techniques. Among many methods, Balanced Truncation is a popular method for constructing a reduced order model. In the heart of Balanced Truncation methods, a sequence of projected generalized Lyapunov equations has to be solved. In this article we present a general framework for the numerical solution of projected generalized Lyapunov equations using preconditioned Krylov subspace methods based on iterates with a low-rank Cholesky factor representation. This approach can be viewed as alternative to the LRCF-ADI method, a well established method for solving Lyapunov equations. We will show that many well-known Krylov subspace methods such as (F)GMRES, QMR, BICGSTAB and CG can be easily modified to reveal the underlying low-rank structures.

Matthias Bollhöfer, André K. Eppler

Backmatter

Titel: System Reduction for Nanoscale IC Design
herausgegeben von: Peter Benner
Verlag: Springer International Publishing
Electronic ISBN: 978-3-319-07236-4
Print ISBN: 978-3-319-07235-7
DOI: https://doi.org/10.1007/978-3-319-07236-4