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Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2011 | OriginalPaper | Buchkapitel

4. The RISPP Run-Time System

verfasst von : Lars Bauer, Jörg Henkel

Erschienen in: Run-time Adaptation for Reconfigurable Embedded Processors

Verlag: Springer New York

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Abstract

This chapter presents the novel run-time system of the RISPP architecture. It exploits the novel concept of modular special instructions (SIs) [BSKH07], as described in Chap. 3. The first section will present a short overview of the RISPP architecture. The focus of that section is placed on describing those parts of the architecture that are required to understand the run-time system. The entire RISPP architecture including the novel computation and communication infrastructure [BSH08a] is described in Chap. 5. The second section analyses the requirements of the run-time system, provides a first overview of its tasks, and describes how these tasks interact, using a state-transition diagram [BSH08b].

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Vorheriges Kapitel Modular Special Instructions
Nächstes Kapitel RISPP Architecture Details
Fußnoten
1
For instance, depending on the number of ports of the register file.
 
2
It does not need to be determining yet which opcode shall correspond to which SI; just opcodes for SIs need to be reserved.
 
3
For example, by calling the SI using inline assembly or by modifying the compiler to automatically use it.
 
4
That is, the tool that creates binary code out of assembly code needs to know which instruction format and opcode shall be used for an SI that occurs in the assembly code.
 
5
At least one atom needs to be loaded which lasts approximately 1 ms.
 
6
Typically only one reconfiguration port is available.
 
7
Note: in general, the FBs may additionally contain forecasts for further SIs.
 
8
Both demand a multiplication.
 
9
The fine-tuning actually works on the number of SI executions and not on the number of MBs that are shown here for simplicity.
 
10
Altogether, 1,024 entries are reserved for all possible SI opcodes, see Sect. 5.​1.
 
11
Typically at the cost of slower molecules for other SIs executing in the same hot spot.
 
12
That is, those atoms that are currently loaded into an atom container.
 
13
The actual reconfiguration time might be longer if the atoms of another SI are loaded in between (see Sect. 4.5).
 
14
Considering latency improvement and reconfiguration delay.
 
15
That is, the atoms of the explicitly selected molecules.
 
16
The smallest reconfiguration delay is not used here, because it is 0 if the reconfiguration finishes in time.
 
17
This is the typical case; however, the error of the prediction is typically small.
 
18
The shape of R1–R4 continues when examining larger values of the parameters.
 
19
Please note that the union operator in (4.29) is a set union, not a molecule union, i.e. M’ is a set of molecules not a meta-molecule
 
20
That is, not all demanded atoms are available.
 
21
That is, demanded number of cycles for one execution of the molecule.
 
22
Common intermediate format, i.e., 352 × 288 pixels.
 
23
Slowest execution speed for zero ACs (corresponds to a general-purpose processor): 7,403 million cycles.
 
24
That is, the computations are completed before all demanded atoms are reconfigured.
 
25
That is, already loaded to the reconfigurable fabric.
 
26
Determined by SI forecasting (see Sect. 4.3).
 
27
Determined by molecule selection (see Sect 4.4).
 
28
If all planed reconfigurations finish before the next forecast.
 
Metadaten
Titel
The RISPP Run-Time System
verfasst von
Lars Bauer
Jörg Henkel
Copyright-Jahr
2011
Verlag
Springer New York
Buch
Run-time Adaptation for Reconfigurable Embedded Processors

Print ISBN: 978-1-4419-7411-2

Electronic ISBN: 978-1-4419-7412-9

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4419-7412-9_4

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