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2010 | OriginalPaper | Buchkapitel

11. Time-To-Failure Models for Selected Failure Mechanisms in Integrated Circuits

verfasst von : J.W. McPherson

Erschienen in: Reliability Physics and Engineering

Verlag: Springer US

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Abstract

Advanced integrated circuits (ICs) are very complex, both in terms of their design and in their usage of many dissimilar materials (semiconductors, insulators, metals, plastic molding compounds, etc.). For cost reductions per device and improved performance, scaling of device geometries has played a critically important role in the success of semiconductors. This scaling (where device geometries are generally reduced by 0.7x for each new technology node and tend to conform to Moore’s Law) has caused the electric fields in the materials to rise (bringing the materials ever closer to their breakdown strength) and current densities in the metallization to rise causing electromigration (EM) concerns.

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Vorheriges Kapitel Ramp-to-Failure Testing
Nächstes Kapitel Time-To-Failure Models for Selected Failure Mechanisms in Mechanical Engineering
Fußnoten
1
Moore’s Law, attributed to Gordon Moore, states that the transistor density on ICs tends to double every 18–24 months.
 
2
Recall from Chapter 4 that a flux divergence represents the net flow of material into or out of a region of interest. A flux divergence can result in the accumulation or depletion of metal ions in the region of interest. Microstructure differences, such as grain size differences, can result in flux divergences.
 
3
Vacancy is simply a vacant lattice site. A vacancy represents free space (a missing atom) and, as such, a clustering of vacancies can result in void formation. A discussion of vacancies can be found in Chapter 12.
 
4
Grain boundary (or interface) transport generally dominates for T < 0.5Tmelt, where Tmelt is the melting temperature of the metal (expressed in Kelvin). Bulk (within grain or lattice) transport can dominate for T > 0.5Tmelt. The activation energy for grain boundary transport Qgb is roughly half that of bulk transport Qbulk.
 
5
Grain sizes are not really as regular/uniform as illustrated in Fig. 11.3. Grain sizes are generally lognormally distributed.
 
6
Via is the term used to describe the physical/electrical connection of an upper level of metal to a lower level of metal through a dielectric layer.
 
7
Up (into via) or down (into via) refers to the electron-flow direction.
 
8
Drift and diffusion (backflow) mechanisms were discussed in Chapter 6. If the backflow pressure (created by the accumulation of material) starts to cancel the drift-induced pressure, then net material flow ceases.
 
9
For Al-alloys, stripe widths of approximately 3 μm are typically used for EM testing.
 
10
It is assumed here that the average of the positive pulses is greater than the average of the negative pulses.
 
11
Tabs (extra metal extensions) at the cathode-end connection (acting as a reservoir/source of additional metal ions) can slow down the voiding rate and thus can improve the time-to-failure.
 
12
Jim Black was the first to propose a current density exponent of n=2 for electromigration in Al-alloys, without barrier layers, where the void-nucleation phase tends to dominate the time-to-failure. However, n=2 is not valid for all metal systems, e.g., n=1 is used for Cu metallization.
 
13
The current I, as used here, is a virtual stress (discussed in Section 8.​4) because TF depends strongly on the dimensions of the contact. The use of a real stress, such as current density J(=I/Area), would normally be preferred. However, due to current crowding effects in the small contact window, the current density is very non-uniform and difficult to describe. For this reason, the virtual stress current I is used.
 
14
Joule (or self) heating can be an important issue for contacts. Even though the ambient temperature may be held constant, the actual contact temperature can vary greatly with the current level applied. If the self heating is not properly accounted for, then very high apparent n values are obtained.
 
15
This is normally referred to as plastic (versus elastic) deformation. Elastic deformations tend to produce no damage to the material while plastic deformations tend to cause some amount of permanent change to the material.
 
16
Generally, metals will tend to flow in order to relieve the stress in the material. Unfortunately, such mass flow can result in notching/voiding in the metal.
 
17
Grain boundaries which are nearly perpendicular to the metal stripe length.
 
18
As discussed in Chapter 12, the strain energy reduction/release is greater than the energy increase associated with the creation of new surfaces.
 
19
The metallization on a chip is constrained (fixed strain) due to the hard dielectrics surrounding the metallization. The creep, in this case, is a stress-relaxation mechanism under fixed strain which can lead to void formation.
 
20
This equation is usually referred to as the McPherson and Dunn Model for stress migration in interconnects.
 
21
The prefactor (T0−T), in Eq. 11.6, can be expressed in °C or K, since this is a difference of two temperatures. However, the temperature in the exponential term must be expressed in K.
 
22
The breakdown current is determined by ramping the current to breakdown. If the metal stripe has a notch/void in it, then the breakdown current should be lower.
 
23
On a chip, there can be several levels of metallization, stacked on top of one another with a layer of dielectric in between metal levels. The via is an electrical connection, through the dielectric layer(s), from an upper metal level to a lower metal level.
 
24
The voiding is a stress-relief mechanism as discussed in Chapter 12. Void growth occurs because of vacancy flow due to stress gradients. More vacancies are available in wide Cu-leads versus narrow ones.
 
25
Assembly describes the process used to encapsulate a silicon chip into plastic packaging with electrical connections to the outside world. This process includes: silicon chips are first separated from the wafer (usually by sawing), chips are then attached to a lead frame, the lead frame is then molded in plastic, and finally the leads are trimmed and formed.
 
26
If Al corrosion occurs in a liquid state, the corrosion may have the appearance of simply missing aluminum. If Al corrosion occurs in humidity/moisture, the corrosion product (usually aluminum hydroxide) can be expansive in size and will appear to be black, under an optical microscope, due to its very rough/cracked texture. The volume of the corrosion product, usually Al(OH)3, can be much larger than the volume of Al consumed.
 
27
The corrosion cell is discussed in more detail in Chapter 12.
 
28
The Galvanic Series is discussed in Chapter 12.
 
29
If the ions cannot diffuse away from the region of oxidation/reduction, then a rise in electrical potential will retard the corrosion potential.
 
30
Corrosion activity was measured by monitoring the resistance-rise versus time, for a metal stripe when the test structure was stored in an ammonium-chloride solution.
 
31
100% relative humidity represents saturated water vapor.
 
32
This low value of activation energy (0.3 eV) is typical for wet corrosion mechanisms where the mobility of the diffusing ions is good. Due to a very high concentration of phosphorus in the PSG, liquid droplets of phosphoric acid can develop under humid conditions.
 
33
The phosphorus in the glass is very useful in gettering unwanted sodium ions. The Na-ions, if present, can induce a surface-inversion failure mechanism. The surface-inversion failure mechanism is discussed in Section 11.6.
 
34
Fatigue failure can result from cyclical stresses as discussed in Chapter 12.
 
35
Coffin-Manson model is discussed in more detail in Chapter 12.
 
36
The plastic strain range is outside the normal elastic region. Damage is occurring to the material in the plastic range.
 
37
Additional information on crack propagation can be found in Chapter 12.
 
38
Poly is short for polycrystalline silicon. Doped-poly has been a common electrode material for MOSFETs for many years. Advanced ICs may use metal gate-electrodes.
 
39
The E-Model was originally introduced as an empirical model and was later given a theoretical thermochemical foundation.
 
40
For MOS-type capacitors on silicon, when stressing in accumulation: \(V_{ox} \cong V_{applied} - 1V\). Whereas, when stressing in inversion: \(V_{ox} \cong V_{applied}\).
 
41
The values for η(m, n) can be found in Chapter 12.
 
42
This range is consistent with effective dipole moments: \(p_{eff} (9,2)\) to \(p_{eff} (9,1)\).
 
43
Remember that a hole is simply a missing bonding electron. Hole capture thus eliminates one of the two electrons in the S-O bond. Therefore, hole capture serves to weaken the bond. Furthermore, the hole (if hot) can also bring energy to the bond to help in the bond-breakage process.
 
44
EPROM is an erasable programmable read-only memory.
 
45
EEPROM is an electrically erasable programmable read-only memory.
 
46
Flash Memories are block-erasable EEPROMs.
 
47
Ramped-to-breakdown testing was extensively discussed in Chapter 10. The ramp-to-breakdown test can be a very important test for interconnect dielectric reliability. Both intrinsic issues (low-k integrity) and extrinsic issues (metal/dielectric defects) can be found in a ramp-to-breakdown test at elevated temperature.
 
48
Lucky electron means that it obtains the maximum possible kinetic energy.
 
49
These energetic electrons are referred to as hot, because their kinetic energy is greater than the average thermal energy (3/2)K B T.
 
50
Normally, each Si-O bond has two electrons in it which are being shared. If the bond is broken (thus forming a dangling bond), depending on the chemical potential (Fermi-level), a dangling bond can be neutral (retains a single electron), can become negative with the trapping of a second electron, or can give up its single electron (hole trap) and become positively charged.
 
51
The gate voltage (Vgs) conditions must be determined that produce the maximum substrate current, for a fixed drain-to-source voltage Vds. For an n-type MOSFET, this could be Vgs = (1/2) Vds for n-type MOSFETs with longer channel lengths (>0.25um) but could be Vgs=Vds for devices with shorter channel lengths. In any case, the voltage conditions which produce the maximum substrate current must be established for the full range of expected device operation.
 
52
It is also possible that some of the H+ ions may be reduced and dispersed within the poly gate electrode and/or diffuse laterally from the gate region.
 
53
Note that for the case m=0.25, the time-to-failure kinetics are four times greater than the degradation kinetics !
 
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Metadaten
Titel
Time-To-Failure Models for Selected Failure Mechanisms in Integrated Circuits
verfasst von
J.W. McPherson
Copyright-Jahr
2010
Verlag
Springer US
Buch
Reliability Physics and Engineering

Print ISBN: 978-1-4419-6347-5

Electronic ISBN: 978-1-4419-6348-2

Copyright-Jahr: 2010

DOI
https://doi.org/10.1007/978-1-4419-6348-2_11

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