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2010 | OriginalPaper | Buchkapitel

3. U-MOSFET Structure

verfasst von : B. Jayant Baliga

Erschienen in: Advanced Power MOSFET Concepts

Verlag: Springer US

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Abstract

As discussed in the previous chapter, the first power MOSFET structure commercially introduced by the power semiconductor industry was the double-diffused or D-MOSFET structure. The specific on-resistance of the D-MOSFET devices designed for low blocking voltages was found to be constrained by the significant channel resistance due to the low channel density and the JFET region contribution.

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Literatur
1.
Zurück zum Zitat B.J. Baliga, “Fundamentals of Power Semiconductor Devices”, Springer-Science, New York, 2008.CrossRef B.J. Baliga, “Fundamentals of Power Semiconductor Devices”, Springer-Science, New York, 2008.CrossRef
2.
Zurück zum Zitat J. Zeng, et al, “An Ultra-Dense Trench-Gated Power MOSFET Technology using a Self-Aligned Process”, IEEE International Symposium on Power Semiconductor Devices, Abstract 7.3, pp. 147–150, 2001. J. Zeng, et al, “An Ultra-Dense Trench-Gated Power MOSFET Technology using a Self-Aligned Process”, IEEE International Symposium on Power Semiconductor Devices, Abstract 7.3, pp. 147–150, 2001.
3.
Zurück zum Zitat M. Darwish, et al, “A New Power W-Gated Trench MOSFET (WMOSFET) with High Switching Performance”, IEEE International Symposium on Power Semiconductor Devices, Abstract 1.1, 2003, pp. 100–104. M. Darwish, et al, “A New Power W-Gated Trench MOSFET (WMOSFET) with High Switching Performance”, IEEE International Symposium on Power Semiconductor Devices, Abstract 1.1, 2003, pp. 100–104.
4.
Zurück zum Zitat T. Aoki, et al, “High Performance and Reliability Trench Gate Power MOSFET with Partially Thick Gate Oxide Film Structure”, IEEE International Symposium on Power Semiconductor Devices, Abstract 6.3, pp. 85–88, 2006. T. Aoki, et al, “High Performance and Reliability Trench Gate Power MOSFET with Partially Thick Gate Oxide Film Structure”, IEEE International Symposium on Power Semiconductor Devices, Abstract 6.3, pp. 85–88, 2006.
5.
Zurück zum Zitat H. Wang, et al, “A 70V UMOS Technology with Trenched LOCOS Process to Reduce Cgs”, IEEE International Symposium on Power Semiconductor Devices, Abstract P8-25, pp. 181–184, 2007.CrossRef H. Wang, et al, “A 70V UMOS Technology with Trenched LOCOS Process to Reduce Cgs”, IEEE International Symposium on Power Semiconductor Devices, Abstract P8-25, pp. 181–184, 2007.CrossRef
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Zurück zum Zitat N. Thapar and B. J. Baliga, “Influence of the Trench Corner Design on Edge Termination of UMOS Power Devices”, Solid State Electronics, Vol. 41, pp. 1929–1936, 1997.CrossRef N. Thapar and B. J. Baliga, “Influence of the Trench Corner Design on Edge Termination of UMOS Power Devices”, Solid State Electronics, Vol. 41, pp. 1929–1936, 1997.CrossRef
Metadaten
Titel
U-MOSFET Structure
verfasst von
B. Jayant Baliga
Copyright-Jahr
2010
Verlag
Springer US
DOI
https://doi.org/10.1007/978-1-4419-5917-1_3

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