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Erschienen in:
2016 | OriginalPaper | Buchkapitel
Ultra High-Performance ASIC Implementation of SM2 with SPA Resistance
verfasst von : Dan Zhang, Guoqiang Bai
Erschienen in: Information and Communications Security
Verlag: Springer International Publishing
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Abstract
To ensure secure information exchange, demand for hardware implementation of elliptic curve cryptography (ECC) is increasing rapidly in recent years. In this paper, we propose an ASIC design for ECC over SCA-256 prime field, delivering both high performance and great SPA resistance. For algorithm selection, we integrate calculation simplification into the classic algorithm, Montgomery Powering Ladder (MPL). Based on the deduction of Fast NIST Reduction, we innovatively achieve the configurable modular multiplication module and then the isochronous point addition and double units. Pipeline architecture, execution order optimization and modular design are all applied to improved performance. Evaluated by CMOS standard cell library of 0.13 \(\upmu \)m, this ECC processor costs only 208 \(\upmu \)s and 6.8 \(\upmu \)J for one scalar multiplication and runs at high frequency of 228 MHz with area of 156 k gates. Compared to related works, it is much more advantageous in not only area-time product but also SPA resistant protection.