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Erschienen in:
2009 | OriginalPaper | Buchkapitel
Verifying VLSI Circuits
verfasst von : Mark R. Greenstreet
Erschienen in: Automated Technology for Verification and Analysis
Verlag: Springer Berlin Heidelberg
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Circuit-level verification is a promising area for formal methods research. Simulation using tools such as SPICE remains the main method for circuit validation. Increasing integration densities have increased the prevalence of analog/mixed-signal designs. It is now common for analog components such as DLLs and phase correction circuits to be embedded deep in digital designs, making the circuits critical for chip functional yet hard to test. While digital design flows have benefited from systematic methodologies including the use of formal methods, circuit design remains an art. As a consequence, analog design errors account for a growing percentage of design re-spins. All of these have created a pressing need for better circuit-level CAD and motivated a strong interest in formal verification.