2010 | OriginalPaper | Buchkapitel
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
verfasst von : Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
Erschienen in: High Performance Embedded Architectures and Compilers
Verlag: Springer Berlin Heidelberg
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Customizable processors augmented with application-specific
Instruction Set Extensions (ISEs)
have begun to gain traction in recent years. The most effective ISEs include
Architecturally Visible Storage (AVS)
, compiler-controlled memories accessible exclusively to the ISEs. Unfortunately, the usage of AVS memories creates a coherence problem with the data cache. A multiprocessor coherence protocol can solve the problem, however, this is an expensive solution when applied in a uniprocessor context. Instead, we can solve the problem by modifying the cache controller so that the AVS memories function as extra ways of the cache with respect to coherence, but are
not
generally accessible as extra ways for use under normal software execution. This solution, which we call
Virtual Ways
is less costly than a hardware coherence protocol, and eliminate coherence messages from the system bus, which improves energy consumption. Moreover, eliminating these messages makes Virtual Ways significantly more robust to performance degradation when there is a significant disparity in clock frequency between the processor and main memory.