Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management

This paper presents three different WiFi receiver chain lineups using a high dynamic range continuous time Sigma Delta A/D converter (SD-ADC). The chains tradeoffs are analyzed from the perspective of the ADC design. The key performance indexes are performance, blocker rejection, area and power consumption. Two lineups implement an active filter stage between the mixer and the ADC: one uses a trans-impedance amplifier and the other one a Gm stage. A third lineup avoids the active filtering stage and replaces it with a passive pole. The measurements show that the three lineups achieve the same chain performance and can therefore be directly and fairly compared in the same environment.

The signal bandwidth of delta-sigma analog-to-digital converters has been greatly extended during the last few decades from a few tens of kHz bandwidth for audio to several hundred MHz to date for wireless applications. To enable a wideband and filterless RF radio front-end, high dynamic range and very high linearity of the wideband delta-sigma modulator is required as well. In this chapter the design aspects of high-resolution and wideband continuous-time delta-sigma modulators are presented, from architectural choices to implementation and circuit design examples.

This article reviews the application and the requirements of Sigma-Delta ADCs with improved interferer robustness. While most power efficient state-of-the-art architectures for Sigma-Delta ADCs are based on forward compensated loop filters, these architectures are known to feature gain in their signal transfer function at out-of-band frequencies. In applications, where interferer and blocker signals are present outside the band of interest, gain at these frequencies consequently increases the required dynamic range or the necessary pre-processing complexity, e.g. within the preceding filter stages. More recently, increasing attention was dedicated to improved signal transfer functions of Sigma-Delta ADC’s, such that—by intrinsically attenuating the interferers within the Sigma-Delta loop filter—pre-processing stages can be relaxed or even omitted, and the dynamic range can be reduced. In this contribution, the state-of-the-art of Sigma-Delta ADCs is reviewed with respect to interferer robustness from system level on.

Many signal chains need to digitize signals in the presence of interferers. The usual way of accomplishing this is to use an analog anti-alias filter followed by a Nyquist ADC. Continuous-time \(\varDelta \varSigma\) modulators (CT\(\varDelta \varSigma\) M) are compelling alternatives to Nyquist rate ADCs. While oversampling relaxes the requirements of the anti-alias filter, it is natural to wonder if the built-in filtering of a CT\(\varDelta \varSigma\) M, characterized by its Signal Transfer Function (STF), can be used to attenuate interferers so that an explicit filter up front can be dispensed with altogether. It turns out that the Signal Transfer Function (STF) of a conventional CTΔ ΣM is a by-product of NTF synthesis, with the designer having little control over it. The STF can be independently controlled by using a filter up front—however, this increases power dissipation and degrades linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. This work reviews filtering \(\varDelta \varSigma\) conversion and circuit techniques for such converters.

The smallest, most efficient CT ΣΔ ADCs have typically been feed‐forward (FF) compensated single-bit implementations. However, this has not translated in consumer radio receivers because of poor performance in the presence of out‐of‐band near-blockers and clock jitter. As a result SAR ADCs, filtering, and multi-bit CT ΣΔ ADCs have become increasingly prevalent at the cost of receiver power and area. This paper presents the challenges and design techniques used to restore single-bit FF CT ΣΔ ADC performance and efficiency in the context of a modern consumer radio receiver.

BW = f _s/(2 OSR). As this equation indicates, wideband ΣΔ ADCs having bandwidths in the hundreds of MHz require clock frequencies in the GHz range even to obtain a relatively low OSR of ten. In such low-OSR systems, MASH architectures achieve better power efficiency than traditional single-loop ΣΔ ADCs. Nanometer CMOS process technologies enable continuous-time ΣΔ ADCs operating at GHz clock frequencies. However, the combination of continuous-time and low-OSR at a GHz clock frequency presents new challenges. In this paper, ΣΔ ADCs including the traditional single-loop and MASH, are reviewed in the context of wideband wireless applications with out-of-band blockers. A unique circuit block in continuous-time MASH, a continuous-time residue generation circuit, is discussed in detail. Two wideband MASH implementations in a 28 nm CMOS process are compared and their properties and performances are discussed based on the architectural differences.

Electronics are rapidly becoming the major driver in new car developments. Since their humble beginnings as entertainment and comfort features for the car driver, they have gradually been used to optimize the car behavior and are now more and more taking over the operation of the human driver itself. This is a disruptive evolution since the fully autonomous car will ultimately function as a personal public transport with high comfort and flexibility. Many technical, safety and legal issues have to be solved but this evolution can also have a large impact on traffic and city organization. Due to the large impact of mobility on the human society, it is clear that the future automotive electronics in the autonomous car will have to be very predictable and accurate and must remain extremely reliable and safe under the harsh automotive environment conditions and disturbances.

Power distribution is the overall term for all items bringing electrical power from source to loads. For carmakers power distribution is “the” hot topic in power network (power net) architectures, this is due to the fact that complexity is increasing from year to year driven by new functionality, safety and legal requirements.

This leads to many new high power loads which must be served by the power net. To overcome the current power net limitations a change from relays and fuse to semiconductor is required. The target of new power net architectures is a reduction of cost, power losses and weight of the vehicle.

Semiconductors instead of relays and fuses are “the enabler” for these architecture changes. Optimization on semiconductor or wiring harness level only is not sufficient anymore. To gain more system benefit wiring harness, switches and loads have to be optimized together. Main challenges for semiconductors are increased power capability, precise diagnosis, high reliability and low idle/quiescent currents.

This article covers the design of highly integrated gate drivers and level shifters for high-speed, high power efficiency and dv/dt robustness with focus on automotive applications. With the introduction of the 48 V board net in addition to the conventional 12 V battery, there is an increasing need for fast switching integrated gate drivers in the voltage range of 50 V and above. State-of-the-art drivers are able to switch 50 V in less than 5 ns. The high-voltage electrical drive train demands for galvanic isolated and highly integrated gate drivers. A gate driver with bidirectional signal transmission with a 1 MBit/s amplitude modulation, 10/20 MHz frequency modulation and power transfer over one single transformer will be discussed. The concept of high-voltage charge storing enables an area-efficient fully integrated bootstrapping supply with 70 % less area consumption. EMC is a major concern in automotive. Gate drivers with slope control optimize EMC while maintaining good switching efficiency. A current mode gate driver, which can change its drive current within 10 ns, results in 20 dBuV lower emissions between 7 and 60 MHz and 52 % lower switching loss compared to a conventional constant current gate driver.

This paper presents a low complexity digital self-calibration technique for a successive-approximation-register analog-to-digital converter (SAR ADC) for automotive applications. The ADC includes a digital-to-analog converter (DAC) having a binary, not calibrated, lsb part and a calibrated thermometric msb part. Very few extra elements are required in the analog part due to the self-calibration capability and only a limited amount of logic is added to the digital section.

The calibration sequence is executed once, during the testing process, and the results are stored on the device itself. The calibration process does not need any special precise external equipment.

Sensors are widely used in automotive applications and they are among the most used electronic components in a car. Within the advanced sensing solutions for automotive, the capacitive sensors play a significant role because they can indirectly monitor many different physical quantities with the advantage of a contactless implementation. The design challenge is to implement high performance capacitive sensing solutions, with relatively easy and cheap construction, which can tolerate the harsh automotive electrical and environmental conditions. After a general introduction about sensors in automotive, this work presents several architectures for capacitive sensor interfaces and especially the design aspects to be considered for achieving excellent electromagnetic immunity and emission performance.

This paper presents a low power analog front-end circuit for a 3-axis MEMS capacitive accelerometer. The circuit includes an analog preamplifier to sense the signal coming from the sensor and a successive-approximation A/D converter. Power minimization is achieved by using a continuous-time preamplifier for realizing constant-charge capacitance-to-voltage conversion and a SAR A/D converter with split capacitive array. To cope with potentially large sensor leakage current we used a specific sensor biasing technique, that guarantees ac coupling above 0.1 Hz. The complete analog front-end circuit consumes 90 μW from a single 1.2-V power supply voltage, achieving 65.1 dB of SNR over a 4-kHz bandwidth and − 43. 4 dB of THD.

Switched-capacitor power converters are interesting candidates to realize integrated power converters with acceptable power efficiencies. Depending on the input and output voltage ranges to be accommodated at a desired efficiency, certain voltage conversion ratio(s) need(s) to be implemented. Though the theoretical minimum number of floating capacitors to realize a desired voltage conversion ratio is known, how to actually synthesize the corresponding topologies and what impact these topologies have on circuit performance is less trivial. Besides two-clock-phase topologies, multiple-clock-phase topologies have recently been introduced. This paper gives an overview of various methods to implement desired voltage conversion ratios with two or multiple clock phases and compares their performance under given boundary conditions.

A variety of modern applications spanning portable computing, communications, and even renewable energy demand low-cost, small form-factor power delivery solutions that remain efficient and reliable. This paper provides an overview of resonant and multimode switched capacitor DC-DC converters and discusses their prospects for meeting these challenges. An overview of the constraints that limit performance scaling of conventional magnetic and switched-capacitor converters is provided. A comparison and analytical framework for the resonant multimode approach is given that helps identify where the approach is most practical and effective. Implementation and performance details of recently published work is highlighted, both at the chip and board level.

Ultimate integration of a power converter either means embedding all components in silicon or stacking them closely in a 3D arrangement. High switching frequency is a straightforward approach for reducing the values of passive devices. Silicon integration is the natural approach for switched-capacitor converters but still fails for inductive converters because of the magnetic devices, especially when a magnetic material is involved, what is the case for high power density. These latter components may be fabricated in an integrated approach but the fabrication process is not compatible in essence and cost with the silicon process. Heterogeneous integration is then a cost-effective solution. The article details an example of such an heterogeneous fabrication of a step-down converter. A suitable architecture is first selected for high switching frequency and high efficiency operation. Using an advanced silicon node complicates the architecture if the input voltage is much higher than the technology nominal voltage. Experimental measurements are presented that corroborate the simulation. 91 % peak efficiency is demonstrated for a 100 MHz switching frequency buck converter at 3.3 V input voltage, 1.2 V to 2.4 V output voltage and 0–300 mA load current.

Mechanical stress has a notable effect on the parameters of most micro-electronic devices. This leads to inaccuracies and drifts, which are relevant for precision analog circuits. In contrast to built-in stress during wafer manufacturing processes, mechanical stress caused by packaging process shows a marked short and long term drift mainly due to moisture absorption. For economic plastic encapsulated packages with high reliability for automotive applications it seems impossible to avoid the drift of mechanical stress. A cost efficient way to tackle this problem is to measure the mechanical stress on-chip and to compensate for its effects by way of an electronic circuit. The paper explains the main concepts and challenges of these mechanical stress compensation circuits. It shows which classes of circuits are suited for this technique, which are the costs and benefits.

This work presents a 7.5-W output power 96 % efficiency capacitor-free single-inductor 4-channel all-digital integrated DC-DC LED driver in a 0.18 µm technology, with up to 24 V input voltage and 1-A LED current for general lighting. It is based on the use of laterally double-diffused DMOS transistors, which offer LED string isolation without any other external component compared to LDMOS. The single-inductor approach is the smallest possible form factor and lowest BOM for multi-channel LED drivers. More than 90 % efficiency in a wide range of 20 mA in DCM to 500 mA in CCM is presented.

This paper presents an ultra-low-power (1 μW-to-1 mW) and high voltage (5 V-to-60 V input voltage) inductive DC-DC converter to efficiently interface electrostatic energy harvesters. The chip is fully autonomous and includes start-up, shunt regulation, and maximum power point tracking. All these functions are realized with a static consumption of less than 500 nW, while being able to efficiently interface harvesters with an equivalent source resistance between 0.5 MΩ and 25 MΩ.