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Erschienen in:
Regular Versus Irregular TSV Placement for 3D IC Kapitel lesen Erstes Kapitel lesen

2013 | OriginalPaper | Buchkapitel

6. 3D Clock Routing for Pre-bond Testability

verfasst von : Sung Kyu Lim

Erschienen in: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Verlag: Springer New York

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Abstract

Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding. The overall yield of 3D ICs improves with pre-bond testability because manufacturers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3D clock tree design. First, each die needs a complete 2D clock tree to enable pre-bond test. Second, the entire 3D stack needs a complete 3D clock tree for post-bond test and operation. In the case of a two-die stack, a straightforward solution is to have two complete 2D clock trees connected with a single through-silicon-via (TSV). In this chapter, we show that this solution suffers from long wirelength and high clock power consumption. Our algorithm improves on this solution, minimizes the overall wirelength and clock power consumption, and provides both pre-bond testability and post-bond operability with minimum skew and constrained slew. Compared with the single-TSV solution, SPICE simulation results show that our multi-TSV approach significantly reduces the clock power by up to 15.9 % for two-die and 29.7 % for four-die stacks. In addition, the wirelength is reduced by up to 24.4 and 42.0 %.
The materials presented in this chapter are based on [27].

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Vorheriges Kapitel Power Delivery Network Design for 3D IC
Nächstes Kapitel TSV-to-TSV Coupling Analysis and Optimization
Fußnoten
1
In the pre-bond testable clock routing, our algorithm generates zero-skew clock trees based on the Elmore delay model [5]. To obtain accurate clock-related metrics, we then extract the netlist, and report the SPICE simulation results, including delay, skew, slew, and power consumption.
 
2
Note that our clock trees with single and multiple TSVs are simulated under the same Vdd, and the power savings mainly come from the capacitance reduction. Therefore, the efficiency of our algorithm in low power and pre-bond testability apply on different Vdd (e.g., from 1.2 to 1.0 V).
 
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C.J. Alpert, A.B. Kahng, B. Liu, I.I. Mandoiu, A.Z. Zelikovsky, Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3), 241–253 (2003)CrossRef
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Metadaten
Titel
3D Clock Routing for Pre-bond Testability
verfasst von
Sung Kyu Lim
Copyright-Jahr
2013
Verlag
Springer New York
Buch
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Print ISBN: 978-1-4419-9541-4

Electronic ISBN: 978-1-4419-9542-1

Copyright-Jahr: 2013

DOI
https://doi.org/10.1007/978-1-4419-9542-1_6

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