3D Integration for NoC-based SoC Architectures

Three-dimensional (3D) stacking of ultra-thin integrated circuits (ICs) is identified as an inevitable solution for future system miniaturization and functional diversification. 3D integration offers a long list of benefits in terms of system form factor, density scaling and multiplication, reduced interconnection latency and power consumption, bandwidth enhancement, and heterogeneous integration of disparate technologies. In this 3D implementation, thinned IC layers are seamlessly bonded with a reliable bonding medium and vertically interconnected with electrical through strata via (TSV). The objective of this chapter is to discuss performance enhancement as well as new integration capabilities brought about by 3D technology, enabling technology platforms, and potential applications made possible by 3D technology.

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use ECE and ECD to study the limits of performance under different memory distribution constraints of various 2-D and 3-D topologies, in current and future technology nodes. Among other results, our model shows that in a 35 nm technology a 16 stack 3-D system can, as a theoretical upper limit, obtain 3.4 times the performance of a 2-D system (8.8 Tera OPS vs 2.6 TOPS) at 70% reduced frequency (2.1 vs 3.7 GHz) on 1/8 the total area (50 vs 400 mm²).

To meet customer’s product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient. The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new generation of ‘super chips’. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes and physical access limitations. This chapter focuses on the challenges of testing 3D-SICs, and describes for which challenges solutions are already available or emerging. It provides an overview of the manufacturing steps of TSV-based 3D-SICs, as far as relevant for testing. Subsequently, it discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.

This chapter reviews the process of 3DIC designing exploiting Through Silicon Via (TSV) technology. The chapter introduces the notion of re-architecting systems explicitly to exploit high density TSV processes. A particular focus is on (redesigned) memory on top of logic. This article also serves as a tutorial for the design of 3D specific systems.

The manufacturing of integrated systems in multiple physical planes provides new opportunities for on-chip interconnection networks. Topologies of networks on-chip that have been of limited use due to the long and, therefore, slower interconnects can now be efficiently implemented in a vertically integrated circuit. Three-dimensional meshes are, reasonably, the first to be explored due to the simplicity of these topologies. Considerable improvements in delay and power can result from these topologies. These improvements originate either from the shorter interconnects or the decrease in the number of switches that data packets traverse to reach the destination network node. To evaluate the benefits obtained by a 3-D mesh on-chip network, appropriate latency and power models are described in this chapter. The accurate evaluation of the performance of these networks should be augmented by temperature-aware models that incorporate the power consumed by the processing elements of the network in addition to the power of the network links and switches. A methodology that includes these models is employed to determine the interconnect architecture within the PEs in each physical plane of a 3-D on-chip network.

The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. This chapter quantifies the performance of 3D NoC architectures. It demonstrates functionality in terms of throughput, latency, energy dissipation, and wiring area overhead. It also addresses the temperature concerns that are apparent in 3D integrated circuits in general as well as many emerging 2D applications, showing that the characteristics of 3D NoCs limit what would otherwise be a dramatic increase in temperature, and in a certain case, even reduce temperature.

The shrinking of processing technology in the deep submicron domain aggravates the imbalance between gate delays and wire delays. While a Network-on-Chip systematically tackles this physical issue by differentiating between local and global interconnects, 3D-Integration by folding the die into multiple layers and using short vertical links instead of long horizontal interconnects, leads to a considerable reduction in the length and the number of long global wires. This chapter elaborates on the strategic exploitation of these two key technologies, where the use of the third dimension in the design of the integrated networks provides a major improvement in the network performance. It makes a case for using asynchronous circuits to implement 3D-NoCs. We claim that asynchronous logic allows benefiting from serialized vertical link leading to the definition of innovative architectures which can address some critical issues of 3D integrated circuits using Through-Silicon-Vias. This allows complying with the cost-efficiency trade-off of the 3D-Integration paradigm.

The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging Systems-on-Chip (SoC) design paradigms based on Networks-on-Chip (NoC) interconnection architectures to 3D chip designs. In this chapter, we consider the problem of designing application-specific 3D-NoC architectures that are optimized for a given application. Both unicast and multicast traffic flows are supported. We present novel 3D-NoC synthesis algorithms that make use of accurate power and delay models for 3D wiring with through-silicon vias. In particular, we present a very efficient 3D-NoC synthesis algorithm called Ripup-Reroute-and-Router-Merging (RRRM), that is based on a rip-up and reroute formulation for routing flows and a router merging procedure for network optimization. Experimental results on 3D-NoC design cases show that our synthesis results can on average achieve significant improvements over regular mesh-based 3D implementations, both in terms of power consumption as well as hop counts.

Three-dimensional integrated circuits are a promising approach to push beyond the integration issues and IO bottlenecks of current Systems on Chips (SoCs). Designing the system interconnect for SoCs with many cores is already a challenge for conventional 2D ICs. The degree of freedom offered by the third dimension makes system interconnect design even more complicated and requires a scalable and predictable architecture for the interconnect, in order to achieve design closure. Networks on Chip (NoCs) was presented as a scalable and predictable architecture for system interconnect and therefore is a necessity for 3D integration. Designing an efficient NoC fabric that satisfies performance requirements, but also meets the constraints imposed by 3D technology, is a significant challenge. In this chapter, we move from an overview of communication requirements for current and future SoC platforms, and we analyze through-silicon-via (TSV) vertical interconnection technology, which is emerging as the most promising technology enabler for 3D integration. We then present methodologies and tools for automated 3D interconnect design, focusing on application-specific NoC synthesis for 3D ICs. 3D-NoC synthesis consists of finding the best NoC topology for the application, computing paths for the communication flows, assigning network components on to the layers of the 3D stack, and placing them in each layer. Experiments, performed on several SoC benchmarks demonstrate that 3D-NoCs with application specific tuning bring significant advantages in communication efficiency, power and delay.

In this chapter, we focus on 3-D Network-on-Chip (NoC) architecture that uses a wireless inductive coupling for vertical interconnection. Because chips are wirelessly connected, the addition, removal, and swapping of known-good-dies in a package are possible after fabrication. We introduce a 3-D NoC architecture that can exploit this flexibility. Then, we introduce a 3-D dynamically reconfigurable processors called MuCCRA-Cube, as an implementation example of the wireless 3-D architecture.

This chapter investigates the architectural design of a 3D die-stacked Graphics Processing Unit. The investigation includes a discussion of the design space of the system as well as some empirical results that quantify the expected performance gain of such a system. Also, the chapter discusses the cost, power and thermal aspects of the proposed designs.