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Erschienen in:
2011 | OriginalPaper | Buchkapitel
A Combined Arithmetic Logic Unit and Memory Element for the Design of a Parallel Computer
verfasst von : Mohammed Ziaur Rahman
Erschienen in: Algorithms and Architectures for Parallel Processing
Verlag: Springer Berlin Heidelberg
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Memory-CPU single communication channel bottleneck of the von Neumann architecture is quickly stalling the growth of computer processors. A probable solution to this problem is to fuse processing and memory elements. A simple low latency single on-chip memory and processor cannot solve the problem as the fundamental channel bottleneck will still be there due to the logical splitting of processor and memory. This paper presents that a paradigm shift is possible by combining Arithmetic logic unit and Random Access Memory (ARAM) elements at bit level. This bit level modest ARAM is used to perform word level ALU instructions with minor modifications. This makes the ARAM cells capable of executing instructions in parallel. It is also asynchronous and hence reduces power consumption significantly. A CMOS implementation is presented that verifies the practicality of the proposed ARAM.