Skip to main content

2016 | OriginalPaper | Buchkapitel

13. A Framework for Network-On-Chip Comparison Based on OpenSPARC T2 Processor

verfasst von : G. Causapruno, A. Audero, S. Tota, M. Ruo Roch

Erschienen in: Applications in Electronics Pervading Industry, Environment and Society

Verlag: Springer International Publishing

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Network-on-Chip is gaining interest in these years thanks to its regular and scalable design. Several topologies have been proposed, and there is the need of a general framework for their test, validation and comparison. In this article a framework based on the OpenSPARC T2 processor is presented, where the NoC is used to replace the Cache Crossbar. With the introduction of protocol translators, it is possible to accomodate any NoC inside the T2. Processor regression tests can be used to validate the design and evaluate timing performance.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Tota, S., Casu, M., Ruo Roch, M., Macchiarulo, L., Zamboni, M.: A case study for NoC-based homogeneous MPSoC architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17, 384–388 (2009) Tota, S., Casu, M., Ruo Roch, M., Macchiarulo, L., Zamboni, M.: A case study for NoC-based homogeneous MPSoC architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17, 384–388 (2009)
2.
Zurück zum Zitat Benini, L., De Micheli, G.: Networks on chips: a new soc paradigm. Computer 35, 70–78 (2002)CrossRef Benini, L., De Micheli, G.: Networks on chips: a new soc paradigm. Computer 35, 70–78 (2002)CrossRef
3.
Zurück zum Zitat Quaglio, F., Vacca, F., Castellano, C., Tarable, A., Masera, G.: Interconnection framework for high-throughput, flexible ldpc decoders. In: Proceedings Design, Automation and Test in Europe (DATE), vol 2. (2006) Quaglio, F., Vacca, F., Castellano, C., Tarable, A., Masera, G.: Interconnection framework for high-throughput, flexible ldpc decoders. In: Proceedings Design, Automation and Test in Europe (DATE), vol 2. (2006)
4.
Zurück zum Zitat Condo, C., Martina, M., Masera, G.: Vlsi implementation of a multi-mode turbo/ldpc decoder architecture. IEEE Trans. Circuits Syst. 60(I), 1441–1454 (2013) Condo, C., Martina, M., Masera, G.: Vlsi implementation of a multi-mode turbo/ldpc decoder architecture. IEEE Trans. Circuits Syst. 60(I), 1441–1454 (2013)
5.
Zurück zum Zitat Tota, S., Casu, M., Ruo Roch, M., Rostagno, L., Zamboni, M.: Medea: a hybrid shared-memory/message-passing multiprocessor noc-based architecture. In: Design, Automation Test in Europe Conference Exhibition (DATE) pp. 45–50 (2010) Tota, S., Casu, M., Ruo Roch, M., Rostagno, L., Zamboni, M.: Medea: a hybrid shared-memory/message-passing multiprocessor noc-based architecture. In: Design, Automation Test in Europe Conference Exhibition (DATE) pp. 45–50 (2010)
6.
Zurück zum Zitat Pande, P., Grecu, C., Jones, M., Ivanov, A., Saleh, R.: Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 1025–1040 (2005)CrossRef Pande, P., Grecu, C., Jones, M., Ivanov, A., Saleh, R.: Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 1025–1040 (2005)CrossRef
7.
Zurück zum Zitat Genko, N., Atienza, D., De Micheli, G., Mendias, J., Hermida, R., Catthoor, F.: A complete network-on-chip emulation framework. In: Proceedings Design, Automation and Test in Europe, vol. 1, pp. 246–251 (2005) Genko, N., Atienza, D., De Micheli, G., Mendias, J., Hermida, R., Catthoor, F.: A complete network-on-chip emulation framework. In: Proceedings Design, Automation and Test in Europe, vol. 1, pp. 246–251 (2005)
8.
Zurück zum Zitat Parulkar, I., Wood, A., Microsystems, S., Hoe, J.C., Falsafi, B., Adve, S.V., Torrellas, J.: Opensparc: an open platform for hardware reliability experimentation (2008) Parulkar, I., Wood, A., Microsystems, S., Hoe, J.C., Falsafi, B., Adve, S.V., Torrellas, J.: Opensparc: an open platform for hardware reliability experimentation (2008)
9.
Zurück zum Zitat Pulimeno, A., Graziano, M., Piccinini, G.: Udsm trends comparison: from technology roadmap to ultrasparc niagara2. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20, 1341–1346 (2012) Pulimeno, A., Graziano, M., Piccinini, G.: Udsm trends comparison: from technology roadmap to ultrasparc niagara2. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20, 1341–1346 (2012)
Metadaten
Titel
A Framework for Network-On-Chip Comparison Based on OpenSPARC T2 Processor
verfasst von
G. Causapruno
A. Audero
S. Tota
M. Ruo Roch
Copyright-Jahr
2016
DOI
https://doi.org/10.1007/978-3-319-20227-3_13

Neuer Inhalt