A Parallel Architecture for Transport Systems and Gateways

The use of HSLANs imposes new requirements on transport systems and gateways concerning their performance. Multiprocessor architectures must be considered to increase the performance of those systems.In this paper a flexible parallel architecture suitable for the implementation of high speed transport systems and high speed gateways is presented. It is based on a pipeline of processor-units each implementing an OSI-sublayer. The internal structure of each processor-unit is individual to each sublayer and is based on pipeline and array concepts. The resulting architecture comprises temporal parallelism as well as spatial parallelism.The derived mulitprocessor architecture is flexible, it can be adapted to various communication structures, and it can be implemented using Transputer networks.First prototype implementations of high speed gateways, a parallel MAC-layer bridge and a parallel OSI internetworking protocol, based on this architecture using Transputer networks are described.