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2024 | OriginalPaper | Buchkapitel

A PUF-Based Secure Boot for RISC-V Architectures

verfasst von : Stefano Di Matteo, Luca Zulberti, Federico Cosimo Lapenna, Pietro Nannipieri, Luca Crocetti, Luca Fanucci, Sergio Saponara

Erschienen in: Applications in Electronics Pervading Industry, Environment and Society

Verlag: Springer Nature Switzerland

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Abstract

Recently, there has been a growing interest in Physically Unclonable Functions (PUFs). These electronic circuits possess several key characteristics such as unpredictability and uniqueness that make them particularly attractive for security applications. PUFs offer an appealing solution for secure boot applications, providing a hardware-based mechanism for generating unique cryptographic keys. These keys can be used to encrypt the bootloader and operating system, thereby enhancing security. In this paper, we propose an innovative, secure boot scheme that leverages the functionality and characteristics of a PUF. Our approach eliminates the need for physical storage of the encryption key of the boot code, which enhances security and provides the possibility of securely updating the firmware. We will present an architecture that comprises essential components, along with a demo board on FPGA. The demo board features a general-purpose 64-bit RISC-V-based system that leverages the proposed PUF-based secure architecture, enabling secure boot and firmware update functionalities.

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Literatur
2.
Zurück zum Zitat Baldanzi L, Crocetti L, Di Matteo S, Fanucci L, Saponara S, Hameau P (2019) Crypto accelerators for power-efficient and real-time on-chip implementation of secure algorithms. In: 2019 26th IEEE international conference on electronics, circuits and systems (ICECS), pp 775–778. https://doi.org/10.1109/ICECS46596.2019.8964731 Baldanzi L, Crocetti L, Di Matteo S, Fanucci L, Saponara S, Hameau P (2019) Crypto accelerators for power-efficient and real-time on-chip implementation of secure algorithms. In: 2019 26th IEEE international conference on electronics, circuits and systems (ICECS), pp 775–778. https://​doi.​org/​10.​1109/​ICECS46596.​2019.​8964731
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Zurück zum Zitat Liu, Y., Briones, J., Zhou, R., Magotra, N.: Study of secure boot with a fpga-based iot device. vol. 2017-August, p. 1053 - 1056 (2017). https://doi.org/10.1109/MWSCAS.2017.8053108, https://www.scopus.com/inward/record.uri?eid=2-s2.0-85034084065 &doi=10.1109%2fMWSCAS.2017.8053108 &partnerID=40 &md5=9cba3d9340f4b2807acc0ab560f9da3f cited by: 24 Liu, Y., Briones, J., Zhou, R., Magotra, N.: Study of secure boot with a fpga-based iot device. vol. 2017-August, p. 1053 - 1056 (2017). https://​doi.​org/​10.​1109/​MWSCAS.​2017.​8053108, https://​www.​scopus.​com/​inward/​record.​uri?​eid=​2-s2.​0-85034084065 &doi=10.1109%2fMWSCAS.2017.8053108 &partnerID=40 &md5=9cba3d9340f4b2807acc0ab560f9da3f cited by: 24
9.
Zurück zum Zitat Nannipieri P, Matteo SD, Baldanzi L, Crocetti L, Zulberti L, Saponara S, Fanucci L (2022) Vlsi design of advanced-features aes cryptoprocessor in the framework of the european processor initiative. IEEE Trans Very Large Scale Integr (VLSI) Syst 30(2):177–186. https://doi.org/10.1109/TVLSI.2021.3129107 Nannipieri P, Matteo SD, Baldanzi L, Crocetti L, Zulberti L, Saponara S, Fanucci L (2022) Vlsi design of advanced-features aes cryptoprocessor in the framework of the european processor initiative. IEEE Trans Very Large Scale Integr (VLSI) Syst 30(2):177–186. https://​doi.​org/​10.​1109/​TVLSI.​2021.​3129107
13.
Metadaten
Titel
A PUF-Based Secure Boot for RISC-V Architectures
verfasst von
Stefano Di Matteo
Luca Zulberti
Federico Cosimo Lapenna
Pietro Nannipieri
Luca Crocetti
Luca Fanucci
Sergio Saponara
Copyright-Jahr
2024
DOI
https://doi.org/10.1007/978-3-031-48121-5_13