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The Journal of Supercomputing

Erschienen in:

01.12.2012

A star network approach in heterogeneous multiprocessors system on chip

verfasst von: Chao Wang, Xi Li, Junneng Zhang, Xuehai Zhou, Aili Wang

Erschienen in: The Journal of Supercomputing | Ausgabe 3/2012

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Abstract

Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA.

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Titel: A star network approach in heterogeneous multiprocessors system on chip
verfasst von: Chao Wang
Xi Li
Junneng Zhang
Xuehai Zhou
Aili Wang
Publikationsdatum: 01.12.2012
Verlag: Springer US
Erschienen in: The Journal of Supercomputing / Ausgabe 3/2012
Print ISSN: 0920-8542
Elektronische ISSN: 1573-0484
DOI: https://doi.org/10.1007/s11227-012-0810-x

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