Active dv/dt filter with SiC MOSFET—interlock-delay effect on the overvoltage at motor terminals

WBG semiconductors promise a profound change in power conversion. Among several advantages, the high switching speed of WBG devices allows reducing the size of passive filters.

Based on this characteristic, Silicon Carbide (SiC) MOSFETs, an example of WBG devices, can execute very narrow (< 300 ns) pulse patterns. This can be used to create an additional pulse sequence at each edge of the fundamental PWM at the inverter output. This additional pulse pattern requires just a small LC filter and significantly reduces the dv/dt at the cable input and, thus, at the motor terminals. Faster SiC MOSFETs show less risk of unwanted oscillations, which may occur due to interlock-delay. Much slower Silicon (Si) IGBTs require interlock-delay during the same time period as the additional pulse patterns and, thus, an interlock-delay compensation to mitigate the overvoltage. After presenting the principle of this approach, called Active dv/dt filter (ADVDTF), and a method to determine the pulse pattern, this paper assesses the overvoltage at motor terminals connected to a long cable (150 m) with SiC MOSFETS without interlock-delay compensation. It presents the results of a simulation and of an experimental test with a 1200 V SiC MOSFET power stage.