Background
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State-of-the-art pipelining techniques in chip multi-processors (CMP) design are utilized and simulated, and their power and performance results are presented. It should be noted that so far, these techniques have mostly been tested on simple and well-known theoretical functions. To the best of our knowledge, earlier studies on power and performance on real time implementation are rare.
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A mathematical model for the evaluation of the proposed approach is introduced, and then solved using a software program execution of code.
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Different aspects of the power-performance efficiency are compared against each other using the existing techniques, and four performance metrics.
Related works
Analytical modeling
Power-performance vs. pipeline stage unification degree
Energy reduction with VSP
Proposed low power architectural technique
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The full-time clock signal is always active regardless of the unification.
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The part-time clock signal is deactivated when the pipeline stages are unified. It is active when they are not unified.
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The unification signal indicates the pipeline stage unification. Since the pipeline register between two adjacent combinatorial logic circuits is inactive or by-passed, the two logic circuits operate together as a single stage.
Experimental modeling
Parameters | Alpha 21264 processor |
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Fetch, issue, commit-width | 4,4 (int), 2 (float), 11 |
Reorder buffer size | 80 |
Issue window | 20 (int), 15 (float) |
Load/store queue | 32 (load), 32 (store) |
Register file | 160 |
Floating-point ALU | 1 adder, 1 multiplier |
Integer ALU | 4 adder, 4 multiplier |
L1 Data, instruction-cache | 512642 |
Dtlb, Itlb | 164128, 132128 (fully associative) |
Clock frequency rate f(\(\beta _1=1\), \(\beta _2=1.5\), \(\beta _3=2\)) | 100 %, 66.7 %, 50 % |
Results of VSP and optimum analysis
IPS | E-Metric | EDP | ED\(^2\)P | ||||
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No. of cores | VSP degree | No. of cores | VSP degree | No. of cores | VSP degree | No. of cores | VSP degree |
2 | 2 | 2 | 1 | 2 | 1 | 2 | 2 |
4 | 1.5 | 4 | 1 | 4 | 1 | 4 | 1.5 |
8 | 1.25 | 8 | 1.25 | 8 | 1.25 | 8 | 1.25 |
16 | 0 | 16 | 1.5 | 16 | 2 | 16 | 0 |
32 | 0 | 32 | 2 | 32 | 3.5 | 32 | 0 |