An integrated machine code monitor for a RISC-V processor on an FPGA

This paper proposes an integrated machine code monitor (iMCM) written in a hardware description language (HDL) and implemented in an FPGA together with a processor. The iMCM reconfigures monitor functions to be provided according to the verification progress of the processor design and the development situation of basic programs. The iMCM was implemented in the FPGA together with the processor as hardware synthesized from HDL description for requested iMCM functions. The iMCM was implemented its functions based on survey questionnaire result for six developers of some processors in FPGAs. And, its correct operation was confirmed by simulation and evaluation using FPGA devices. RISC-V was adopted as an ISA of the target processor. A subset composed of 27 instructions of the compression type instruction set extension with 16-bit instruction word length among RISC-V was employed. All state machines and sequential processes were written in Verilog HDL and implemented together with the processor core as a single circuit by circuit synthesis, placement, and routing. A 41% LUT was added to the implementation of the iMCM against the simple processor implementation. This addition depends on the monitor function to be selected and reconfigured. Furthermore, the iMCM programmed in the FPGA was confirmed to operate at 100 MHz with the circuit mounted on an FPGA evaluation board.