Analysis and performance evaluation of a three-phase sparse neutral point clamped converter for industrial variable speed drives

Because of its cascaded structure, the SNPCC offers a total of \(2^2 \! \cdot 2^3 \!= \!32\) conduction states [9]. While 18 of these combinations effectively apply a nonzero 3-\(\Phi \) line-to-line output voltage (denominated active states), the remaining 14 combinations force a short-circuit of the 3-\(\Phi \) output (denominated zero states). To avoid DC-link short circuits, only the combinations reported in Fig. 2a, b and c are allowed for the 3-L SM. Additionally, for reasons that will be clarified in Sect. 3, the 2-L inverter zero states are not considered, thus the total count of zero states reduces to 6.

The converter states can be unequivocally identified by the 5 bridge-leg switching functionsBy leveraging the relation between switching functions and bridge-leg voltages, the space vector representation of Fig. 2d can be finally obtained [9]. The main role of the 3-L SM is to synthesize the amplitude of the reference voltage vector \(\vec {V}^*\), while the role of the 2-L inverter is to establish its direction. Three kinds of space vectors are identified and categorized according to their amplitude: zero vectors, small vectors with amplitude \(V_{\text {dc}}/3\) and large vectors with amplitude \(2V_{\text {dc}}/3\). The main difference between the SNPCC and standard 3-L inverters is the absence of medium vectors [18], which translates in a lower number of active states (18 against 24) and slightly higher switching frequency output voltage distortion.

For symmetry reasons, the converter operation can be completely analyzed inside a 60\(^\circ \)-wide interval of a 3-\(\Phi \) output period, i.e. a sector; sector is illustrated in Fig. 2e. Each sector can be divided in two main areas: area delimited by zero and small vectors, and area delimited by small and large vectors. The switching functions corresponding to the space vectors of sector are reported in Table 1. It can be observed that small vectors are redundant, since they can all be obtained with either of the two complementary states represented in Fig. 2b, both ensuring \(\ v_\text {hl} = V_\text {dc}/2.\)

Defining the converter modulation index \(M = 2V^*/V_{\text {dc}}\), reporting the reference space vector angle \(\vartheta \) in a \([{0}{},{60}^\circ ]\) window and leveraging simple geometrical relations, the dwell-time expressionsare obtained in sector , whereand the modulation index boundary between area and area isThe dwell-time calculation in area assumes that no small or large vector can be avoided in a switching sequence. Even though area could be divided into sub-regions to reduce the minimum number of space vector transitions in a switching period [12], this would increase the degrees of freedom in the modulation strategy definition and considerably complicate the PWM and control processes, hence it is not considered herein.

In order to ensure a symmetric 3-L characteristic and a limitation of the blocking voltage stress on the 3-L SM switches to half of the total DC input voltage, the voltages \(V_\text {pm}\) and \(V_\text {mn}\) across the two series connected DC-link capacitors must be balanced [19], as described in the following.

The 2-L inverter rail currentallows to derive the 3-L SM rail currentswhich are summarized in Table 1 (for sector ). Only the small vectors affect the mid-point current \(i_\text {m}\). In particular, the redundant vectors (\(V_{\text {S1,P}}/V_{\text {S1,N}}\) and \(V_{\text {S2,P}}/V_{\text {S2,N}}\)) have an equal and opposite effect on \(i_\text {m}\), allowing to balance the DC-link capacitor voltages \(V_\text {pm}\) and \(V_\text {mn}\). If both redundant small vectors are used, the mid-point current local average (i.e. mean value over a switching period) in sector iswhere \(\alpha \in [0, \, 1]\) is a control parameter which defines the dwell-time of the positive small vectors, i.e. \(V_\text {S1,P}\) and \(V_\text {S2,P}\), relative to the total small vector dwell-times \(\delta _\text {S1}\) and \(\delta _\text {S2}\), respectively. In nominal operating conditions \(\alpha =0.5\) yields \(i_{\text {m,AVG}}=0\).

The converter 3-\(\Phi \) output voltage derives from the superposition of both the 3-L SM and the 2-L inverter switching functions. Considering a balanced mid-point voltage \(V_\text {pm}=V_\text {mn}=V_\text {dc}/2\),is obtained. The DM component of \(v_\text {xm}\) defines the output voltage fundamental applied to the driven machine and the switching frequency voltage harmonics resulting in the phase current ripple (see Sect. 4), therefore it must be separated from the CM contribution. A straightforward approach considers the 3-L SM and 2-L inverter separately. The 3-L SM equivalent circuit is illustrated in Fig. 3a, where the virtual point \(\mathrm {m}\)’ is defined for the purpose of separating the DM and CM voltage sources intoThe 2-L inverter equivalent circuit is shown in Fig. 3b, where a second virtual point is arbitrarily defined coincident with \(\mathrm {m}\)’. Both DM and CM contributions depend on \({v_\text {hl}= 2 \, v_{\text {DM,M}}}\), in particularFinally, the total DM and CM voltages can be derived from (14)–(17), obtainingA summary of the DM and CM output voltages in sector is provided in Table 2. The DM voltage waveform \(v_\text {DM,x}\) is composed of 5 levels in area and 6 levels in area , while the CM waveform \(v_\text {CM}\) shows 5 levels in area and 4 levels in area .

An example of the converter switching functions and voltage waveforms in area is provided in Fig. 4, where \(M \! = \! 1\) is considered. These waveforms are obtained by ordering the space vectors according to a generic switching sequence (i.e. sequence U, see Sect. 3) and translating them into a pulse pattern in the time domain. It can be visualized that the 2-L inverter switching functions (\(s_\text {a}\), \(s_\text {b}\) and \(s_\text {c}\)) are alternately clamped either to 0 or 1 for two-thirds of the fundamental period, as in the 1/3 Modulation [20]. This behavior derives from avoiding the 2-L inverter zero states, which allows to switch only one inverter bridge-leg in each sector. To achieve 3-\(\Phi \) sinusoidal (in local average) output voltages, the 3-L SM operates such that the local average of \(v_\text {hl}\) follows the 3-\(\Phi \) rectified line-to-line output voltage fundamentals. In other words, in each sector, the 3-L SM sets the desired voltage between the two clamped phases, leaving to the third inverter bridge-leg the regulation of the two remaining 3-\(\Phi \) line-to-line output voltages [20].

The local averages of \(v_\text {CM}\) and \(v_\text {xm}\) are the same as for the conventional space vector modulation, independently on the selected modulation strategy. This is because switching sequence U and all sequences described in Sect. 3 must include every available non-zero state and equally distribute the dwell-time between redundant small space vectors, thus yielding the same 3-\(\Phi \) output voltage local average as a conventional 2-L inverter. Differently from 2-L and other 3-L inverters, the dwell-time allocation of the zero states does not influence the CM voltage, since both \(V_\text {Z1}\) and \(V_\text {Z2}\) result in \(v_\text {CM}={0}\hbox {V}\).

The focus over a switching period in Fig.  4b provides insight into the selected switching sequence and allows to verify the DM and CM voltage levels listed in Table  2.

To conclude, the generated 3-\(\Phi \) sinusoidal output and mid-point current waveforms with unity power factor (\(\cos \varphi \! = \! 1\)), i.e. ohmic load behavior, are illustrated in Fig.  5. The value of the machine phase inductance (acting as filtering element) is selected to achieve a 30% maximum peak-to-peak current ripple during a 3-\(\Phi \) output period. While \(i_\text {m}\) continuously jumps between two 3-\(\Phi \) sinusoidal output currents and 0\(\hbox {A}\), its local average is 0\(\hbox {A}\) during the complete 3-\(\Phi \) output period. This behavior is maintained for all values of \(\cos \varphi \), since complementary redundant small vectors are always opportunely applied, as explained in Sect.  3.

The DM voltage-time area applied to the machine phases generates a switching frequency flux linkage ripple, which translates in a current ripple inversely proportional to the machine phase inductance L. This ripple is directly responsible for the high-frequency winding and iron losses in the machine itself [21], thus representing a first performance indicator of the adopted modulation strategy.

The current ripple of phase x is found by integrating the high-frequency component of the DM voltage \(v_{\text {DM,x,hf}}\), i.e. subtracting the local average from \(v_\text {DM}\), asThis modeling approach has been adopted and experimentally validated in [22], demonstrating a high level of accuracy.

A highlight of the output current ripple waveforms is provided in Fig. 10, assuming \(M \! = \! 0.85\). To generalize the results, the normalization factoris introduced [23] and the current ripple waveforms are expressed in normalized form. It is worth observing that some asymmetric switching sequences (e.g. 8, 6, A) yield a current ripple envelope that lacks half-wave symmetry, thus featuring an output current spectrum with even order switching harmonics, neverthless, these harmonics do not affect the low-frequency sinusoidal output current shape.

To take into account the complete \({3{\text {-}}\Phi }\) output period, the total RMS current ripple is considered as performance index. Its value can be derived by averaging the RMS current ripple contributions of all three phases over one sector asIt is easily proven that \(\Delta I_\text {RMS}\) is independent on the starting vector of the switching sequence. Separate \(\Delta I_\text {RMS}\) analytical expressions can be derived for area and area , as described in Appendix  1. Therefore, to ensure the continuity of the results over the complete modulation index M range, the merging procedure previously described is applied.

The normalized total RMS current ripples generated by the different modulation strategies are reported in Fig.  11. A best performing sequence cannot be identified over the full operating range, since \(\Delta I_\text {RMS}\) depends on M. Nevertheless, an overall satisfactory trend is offered by sequence 8, which yields the lowest \(\Delta I_\text {RMS}\) value for high modulation indices.

Disregarding the switching frequency current ripple, the RMS current flowing into each DC-link capacitor in balanced conditions is not affected by the modulation strategy, since it only depends on the space vector dwell-times, as discussed in the following. Leveraging the sector periodicity, the expressions for the DC-link upper-rail current \(i_\text {p}\), i.e.are obtained, where, focusing on sector ,Therefore, the same DC-link capacitor RMS current as for conventional 2-L and 3-L inverters results [24, 25], i.e.Even though \(I_{C_\text {dc},\text {RMS}}\) is independent on the modulation strategy, the voltage ripple on \(C_\text {dc}\) generally depends on the switching sequence itself. Nevertheless, since all the strategies considered in this work force a zero mid-point current local average, no low-frequency mid-point voltage ripple is present, making a comparison between switching sequences unnecessary in these regards.

As discussed in Sect.  4, the performance of the switching sequences is summarized by \(\Delta I_{\text {RMS}}\) in Fig.  11 and \(E_ {\text {sw}}\) in Fig.  14. To compare them, an appropriate switching frequency \(f_\text {sw}\) is selected for each sequence to equalize the switching losses in nominal operating condition. Since \(\Delta I_\text {RMS}\) is inversely proportional to \(f_\text {sw}\), this process allows to obtain a single normalized performance index, providing a clear relative comparison between modulation strategies.

This comparison is performed assuming nominal operating conditions (i.e. \(M \! = \! 0.85\), \(\cos \varphi \! = \! 1\)) and the results are illustrated in Fig.  15a, where lower index values translate into better performance. Figure  15b and c report the adjusted switching frequency values of both converter stages and the switching loss distribution between the 3-L SM and the 2-L inverter, respectively. It is shown that the relation between the switching frequency of a converter stage and its switching losses is not straightforward, as the results are also affected by the switched current and voltage values (see Appendix  2).

Overall, the best performing switching sequence in the considered working point is the asymmetric sequence 8. Even though sequence S shows similar performance, i.e. achieving the best results among symmetric sequences, it features wider variations of \(\Delta I_\text {RMS}(M)\) (see Fig.  11) and \(E_\text {sw}(\varphi )\) (see Fig.  14) with respect to sequence 8, thus leading to a larger converter oversizing if a wide range of operating points needs to be covered.

Depending on the operating point of the SNPCC, the current flowing through the semiconductor devices can be unevenly distributed, as shown in Fig.  13. This, together with the different conduction and switching characteristics of IGBTs and diodes, can lead to the unbalanced loading of certain devices. Therefore, the required chip area for each semiconductor device is investigated herein.

The basic concept behind the described chip area minimization procedure is to adapt the chip size of each semiconductor device based on its power losses, aiming to comply with a predefined maximum operating junction temperature. For instance, devices which are subject to higher current stresses require a larger chip size to reduce both the differential electrical resistance (lower conduction losses) and the thermal resistance (improved heat dissipation). Therefore, to quantitatively determine the minimum required chip area, accurate semiconductor loss and thermal models need to be defined.

The conduction characteristics of IGBTs and diodes are approximated as in Fig.  12. Considering R inversely proportional to the chip area A leads to the instantaneous conduction losseswhere i is the conducted current and \(R^*\) is the IGBT/diode specific differential resistance (actual resistance multiplied with the chip area, which results in an area-independent characteristic figure, as known from unipolar power transistors [29]). By substituting in (35) the average and RMS current values derived in Sect.  4, the average conduction losses \(P_\text {cond}\) are obtained.

The selected switching loss model is described by (33) and (34), which assumes that all losses occur inside the IGBT. The proportionality terms \(k_\text {on}\), \(k_\text {off}\) and k are considered to be independent on A, as assumed in [6] and [30]. The average switching losses of a single device can be calculated numerically by identifying all hard turn-on and turn-off transitions within a \({3{\text {-}}\Phi }\) output period \(T = 1/f\), together with the switched voltage \(V_\text {sw}\) and current \(i_\text {sw}\) values, aswhere \(N_\text {on}\) and \(N_\text {off}\) are respectively the number of hard turn-on and turn-off commutations of the considered device within T. It is important to separately calculate the switching losses for each device, since asymmetrical switching sequences can lead to an uneven loss distribution between devices of the same bridge-leg.

The junction-to-heatsink thermal resistance \(R_\text {th}\) model accounting for heat-spreading proposed in [31], i.e.is finally considered. Each semiconductor junction temperature can thus be calculated aswhere \(T_\text {hs} \! = \! {80}^\circ \hbox {C}\) is the heatsink temperature and \(P_\text {tot} = P_\text {cond} + P_\text {sw}\) is the average power loss in each device.

Leveraging these chip area dependent loss and thermal models, the algorithm used for determining the minimum required chip size illustrated in Fig.  16 is adopted. The semiconductor loss parameters \(V_\text {th}\), \(R^*\) and k provided in Table  5 are obtained by statistical fitting of the conduction and switching characteristics of the latest generation \({600} /{1200}\,\hbox {V}\) Trench and Field-Stop IGBTs and fast-recovery emitter-controlled diodes from Infineon [28]. Since these parameters are temperature dependent, the maximum admitted semiconductor junction temperature \(T_\text {j,max} = {125} ^\circ \hbox {C}\) is assumed as operating temperature from the beginning of the procedure, so that no additional iterative loop is required. A starting chip area value \(A_\mathrm {0} = {4}{{\hbox {mm}}^2}\) is considered due to practical manufacturing and wire-bonding limitations. Then, the chip size dependent electrical and thermal resistances are calculated, and the average conduction and switching losses in the design operating point are derived, leveraging the current stress and switching energy expressions obtained in Sect.  4. Finally, the chip junction temperature is calculated and compared to the maximum admitted value \(T_\text {j,max}\). If the maximum temperature limit is fulfilled, the chip area value is saved and the algorithm is ended, otherwise the chip size is increased and the procedure is repeated.

The chip area minimization algorithm is run for the nominal operating point and different values of \(f_\text {sw}\), selecting the minimum required chip size for each device to operate the converter at \(M \! = \! 0.85\) and \(\cos \varphi \! = \! 1\). By summing all IGBT and diode chip sizes, the total converter chip area is obtained.

Following the described chip area minimization procedure, the SNPCC is compared to the most adopted converter topologies in industrial VSDs, namely the conventional 2-L converter and the 3-L NPC converter.

Figure  17a and b shows the trends of the total RMS current ripple \(\Delta I_\text {RMS}\) and the total semiconductor chip area \(A_\text {S}\) as functions of \(f_\text {sw}\), assuming conventional space vector modulation for the 2-L and the 3-L NPC converters, while considering switching sequence 8 for the SNPCC. The results obtained for the traditional 2-L and 3-L converter topologies are in good agreement with [6]. As a further confirmation of the adopted methodology, the minimum chip sizes obtained for all IGBTs result in device RMS current densities in the range of \({80}{-}{120}~{\mathrm{A}}/\hbox {mm}^{2}\), depending on the semiconductor breakdown voltage (i.e., 600\(\,\hbox {V}\), \({1200}\,\hbox {V}\)) and the switching frequency (i.e., which determines switching losses). This is in close agreement with the typical value of around \({100}\,{\mathrm{A}}/\hbox {mm}^{2}\) at nominal current for IGBTs of these voltage classes [32]. It is observed that the 3-L NPC yields both the minimum \(\Delta I_\text {RMS}\) and the lowest chip area increase with \(f_\text {sw}\). Nevertheless, the SNPCC requires a lower \(A_\text {S}\) at low frequencies, since it features less semiconductor devices. If a conventional 16\(\,\hbox {kHz}\) operating switching frequency is assumed for the 2-L converter, the switching frequencies of the 3-L NPC and 3-L SNPC converters can be adjusted to ensure the same \(\Delta I_\text {RMS}\) stress on the driven machine. This calculation process is graphically illustrated in Fig.  17 and the results are reported in Table 6.

The 2-L converter shows the worst overall performance, as already expected from previous analyses [3, 5, 6]. The 3-L SNPCC instead requires the lowest total semiconductor chip area and offers an efficiency comparable to the one of the 3-L NPC converter. Moreover, due to its lower number of transistors, it requires 2 less gate driver circuits, as well as 6 less diodes, further reducing the total part count and overall complexity. Therefore, the SNPCC represents a promising alternative to traditional industrial VSD solutions, particularly in those applications which require relatively low switching frequency. The results of this analysis substantiate and supplement the findings reported in [9, 10].

To further enhance the performance comparison among the 3-L SNPC switching sequences, the chip area minimization procedure illustrated in Fig.  16 is carried out for all modulation strategies, considering nominal operating conditions. The same approach described in Fig.  17 is adopted, adjusting the switching frequency of each modulation strategy to achieve the same \(\Delta I_\text {RMS}\) as the 2-L converter operated at \({16}\,\hbox {kHz}\). Once the switching frequency is selected, the minimum required chip area for each semiconductor device is identified and the converter losses are calculated. It is worth noting that this comparative evaluation is no longer independent of the converter power level and switching frequency (i.e., as opposed to the normalized comparison reported in Fig.  15), as the converter power level affects the conduction losses and the required chip size, while the selected switching frequency modifies the relative contribution of the switching losses to the total converter loss. Therefore, the results of this comparison do not have general validity but are specific for the considered converter specifications. Figure  18a, b and c shows the adjusted switching frequency \(f_\text {sw}\), the required semiconductor chip area \(A_\text {S}\), and the generated semiconductor loss \(P_\text {semi}\) for all modulation strategies, respectively. The figures also indicate the distribution between the 3-L SM and the 2-L inverter stages. The overall semiconductor efficiency \(\eta _\text {semi}\) is shown in Fig.  18d. As expected from the previous analysis (see Fig.  15), it is found that switching sequence 8 achieves the best performance in terms of converter losses and efficiency, while requiring the minimum semiconductor chip area. Again, switching sequence S achieves similar results to sequence 8 but remains less attractive, as it features larger variations in terms of \(\Delta I_\text {RMS}(M)\) (see Fig.  11) and \(E_\text {sw}(\varphi )\) (see Fig.  14).