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Erschienen in: The Journal of Supercomputing 9/2018

06.04.2017

AnyNoC: new network on a chip switching using the shared-memory and output-queue techniques for complex Internet of things systems

verfasst von: Jia-Yang Lin, Yi-Ting Hsieh, Trong Nghia Le, Wen-Long Chin

Erschienen in: The Journal of Supercomputing | Ausgabe 9/2018

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Abstract

Recently, the Internet of things (IoT) has attracted a lot of attention owing to its versatile applications by enabling numerous things/objects to collect and exchange data via Internet. Despite the promising role of IoT, there exists the problem of integrating many heterogeneous functions into an embedded and complex IoT system. Meanwhile, in the past decade, we have also envisioned a paradigm shift in the embedded system market toward the system on a chip (SoC) by integrating all components into a single chip. But the on-chip communications of IoT systems remain an important and challenging issue. This work proposes a new network on a chip (NoC) switching, AnyNoC, employing the shared-memory and output-queue techniques implemented using the efficient dynamic link list, particularly suitable for the IoT SoC. The proposed high-level design can achieve the optimal performance by sharing the data buffer among all ports and eliminating the head-of-line blocking problem, resulting in a virtual point-to-point characteristic without the interruption of slow devices or congestion conditions in other ports. Moreover, the proposed architecture can minimize the required memory size by virtually sharing all buffers among all ports, resulting in one queue needed for each outbound port and totally N queues are required, where N denotes the number of ports. Therefore, compared to the famous wormhole switching, the proposed NoC architecture features lower cost and higher performance, which can approach the theoretical upper bound. Moreover, for a \(16\times 16\) network, the performance gain of the throughput of the proposed switching compared to the popular wormhole switching is about \(40\%\).

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Fußnoten
1
It will be shown later that the proposed design can outperform the popular wormhole technique under the constraint of the same buffer size. In another viewpoint, to achieve the same performance as the wormhole switching, the proposed design requires less buffer size.
 
2
Ideally, each link can transmit one flit in every cycle.
 
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Metadaten
Titel
AnyNoC: new network on a chip switching using the shared-memory and output-queue techniques for complex Internet of things systems
verfasst von
Jia-Yang Lin
Yi-Ting Hsieh
Trong Nghia Le
Wen-Long Chin
Publikationsdatum
06.04.2017
Verlag
Springer US
Erschienen in
The Journal of Supercomputing / Ausgabe 9/2018
Print ISSN: 0920-8542
Elektronische ISSN: 1573-0484
DOI
https://doi.org/10.1007/s11227-017-2035-5

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