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Erschienen in:
Signal Processing Methods for Light Field Displays Kapitel lesen Erstes Kapitel lesen

2019 | OriginalPaper | Buchkapitel

Application-Specific Accelerators for Communications

verfasst von : Chance Tarver, Yang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro

Erschienen in: Handbook of Signal Processing Systems

Verlag: Springer International Publishing

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Abstract

For computation-intensive digital signal processing algorithms, complexity is exceeding the processing capabilities of general-purpose digital signal processors (DSPs). In some of these applications, DSP hardware accelerators have been widely used to off-load a variety of algorithms from the main DSP host, including the fast Fourier transform, digital filters, multiple-input multiple-output detectors, and error correction codes (Viterbi, turbo, low-density parity-check) decoders. Given power and cost considerations, simply implementing these computationally complex parallel algorithms with high-speed general-purpose DSP processor is not very efficient. However, not all DSP algorithms are appropriate for off-loading to a hardware accelerator. First, these algorithms should have data-parallel computations and repeated operations that are amenable to hardware implementation. Second, these algorithms should have a deterministic dataflow graph that maps to parallel datapaths. In this chapter, we focus on some of the basic and advanced digital signal processing algorithms for communications and cover major examples of DSP accelerators for communications.

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Vorheriges Kapitel High Performance Stream Processing on FPGA
Nächstes Kapitel System-on-Chip Architectures for Data Analytics
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Metadaten
Titel
Application-Specific Accelerators for Communications
verfasst von
Chance Tarver
Yang Sun
Kiarash Amiri
Michael Brogioli
Joseph R. Cavallaro
Copyright-Jahr
2019
Buch
Handbook of Signal Processing Systems

Print ISBN: 978-3-319-91733-7

Electronic ISBN: 978-3-319-91734-4

Copyright-Jahr: 2019

DOI
https://doi.org/10.1007/978-3-319-91734-4_14

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