Area Efficient Fully Programmable Baseband Processors

Multi-mode wireless devices and the ever changing wireless standards have increased the popularity and the use of programmable baseband processors. A large portion of the power consumption in programmable baseband processors arises from memory accesses and control-path overhead. It is for that reason crucial to reduce the control-path overhead and the amount of memory accesses by using efficient yet flexible execution units in the processor. By utilizing the vector nature of most baseband processing algorithms it is possible to achieve multi-GIPS processing performance with a limited power budget. In this paper we present an architecture that uses the vector property to provide a good trade-off between the flexibility of VLIW processors and the efficiency of SIMD processors. Our DSP is based on the Single Instruction stream Multiple Tasks (SIMT) architecture which allows concurrent tasks to be executed on the processor controlled by only a single instruction stream.

The SIMT architecture is demonstrated by the BBP2 processor which has been fabricated using the ST 0.12 micro m process. The BBP2 processor is designed for supporting DVB-T/H, WCDMA, Wireless LAN and WiMAX.