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2001 | OriginalPaper | Buchkapitel

Automatic Abstraction for Verification of Timed Circuits and Systems?

verfasst von : Hao Zheng, Eric Mercer, Chris Myers

Erschienen in: Computer Aided Verification

Verlag: Springer Berlin Heidelberg

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This paper presents a new approach for verification of asynchronous circuits by using automatic abstraction. It attacks the state explosion problem by avoiding the generation of a flat state space for the whole design. Instead, it breaks the design into blocks and conducts verification on each of them. Using this approach, the speed of verification improves dramatically.

Metadaten
Titel
Automatic Abstraction for Verification of Timed Circuits and Systems?
verfasst von
Hao Zheng
Eric Mercer
Chris Myers
Copyright-Jahr
2001
Verlag
Springer Berlin Heidelberg
DOI
https://doi.org/10.1007/3-540-44585-4_16

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