Anzeige
Erschienen in:
2009 | OriginalPaper | Buchkapitel
Cache Controller Design on Ultra Low Leakage Embedded Processors
verfasst von : Zhao Lei, Hui Xu, Naomi Seki, Saito Yoshiki, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano
Erschienen in: Architecture of Computing Systems – ARCS 2009
Verlag: Springer Berlin Heidelberg
Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.
Wählen Sie Textabschnitte aus um mit Künstlicher Intelligenz passenden Patente zu finden. powered by
Markieren Sie Textabschnitte, um KI-gestützt weitere passende Inhalte zu finden. powered by
A leakage-efficient cache controller design targeted on ultra low power embedded processors is proposed. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing the fine-grained run-time power gating technique, such a subset can be dynamically powered-off as a power gated domain. Two simple but effective sleeping control policies are proposed to assure the leakage reduction effect; and to eliminate the impact of wake-up process, a latency cancellation mechanism is also proposed. Evaluation results show, in 90nm CMOS technology, 69% and 64% of leakage power can be reduced for instruction cache controller and data cache controller without performance degradation.