3. Carbon Nanotube Field-Effect Transistors

Excerpt

In the past few decades, the electronics field has witnessed a dramatic miniaturization of transistor elements with the number of transistors on an integrated circuit doubling approximately every 2 years [1‐4]. Innovation and integration of new materials, such as high-κ gate dielectrics, various metals, silicides and nitrides, has been the key for this evolutionary path of CMOS device scaling [1‐4]. Notably, however, the active channel material has predominantly remained the same, mainly owing to the scalability and manufacturability of the Si technology. As the device dimensions, such as the channel lengths approach the sub-10 nm regime, direct tunneling between source (S) and drain (D), and sever short channel effects present a fundamental challenge in continued scaling of Si devices. As a result, tremendous research efforts have recently been undertaken by various academic and industrial research groups for integrating new semiconductors as the channel material to enable (i) more efficient transport of carriers (i.e., higher mobility) and (ii) improved electrostatics at nanoscale (i.e., non-planar channel materials) [5‐7]. In most approaches, a hybrid technology is envisioned, where Si still remains the handling substrate for fabrication processing, heat transport, and mechanical support purposes, with a new semiconductor integrated on the top for enhanced device operations or added new functionalities. One such material is carbon nanotubes. The unique electron transport properties and band structure of nanotubes, as discussed in Chapter 1, and their quasi 1-D geometries make semiconducting SWNTs ideal channel materials for high-speed and low-power electronics [8‐27]. In this chapter, we summarize some of the recent experimental advancements in the field of carbon nanotube transistors and discuss the device physics of 1-D channel materials. In Section 3.2, we discuss the nanotube–metal interface properties and the ability to attain Schottky barrier free contacts by utilizing an appropriate metal material due to the lack of Fermi-level pinning in 1-D junctions. In Section 3.3, we discuss the high-κ gate dielectric integration followed by a presentation on quantum capacitance associated with 1-D materials in Section 3.4. In Sections 3.5 and 3.6, we discuss the role of the molecular species absorbed on the surface of nanotubes in the chemical doping and device hysteresis. Finally, various nanotube transistor structures, including Schottky FETs, MOSFETs, and band-to-band tunneling FETs, are discussed in Sections 3.7–3.9. …