Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Bücher
Zeitschriften
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
MTZ-Fachkongress

Antriebe und Energiesysteme von morgen


Austausch von Automobil- und Energiewirtschaft

Am 14./15. Mai geht es in Chemnitz um die Mobilitätswende durch Elektro- und Wasserstofffahrzeuge.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
From Atoms to Circuits: Theoretical and Empirical Modeling of Hot Carrier Degradation Kapitel lesen Erstes Kapitel lesen

2015 | OriginalPaper | Buchkapitel

Circuit Reliability: Hot-Carrier Stress of MOS Transistors in Different Fields of Application

verfasst von : Christian Schlünder

Erschienen in: Hot Carrier Degradation in Semiconductor Devices

Verlag: Springer International Publishing

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

This work classifies hot-carrier stress (HCS) and negative- & positive-bias temperature instability (N/PBTI) in the larger context of circuit and product aging. The area of conflict regarding the importance of HCS and N/PBTI will be evaluated. Different fields of applications will be discussed. Some typical examples will illuminate in each case if one damage mechanism dominates the degradation. The root cause for the occurring proportion of HCS and N/PTBI will be explained. Specific characteristics of applications, circuits, and operation conditions leading to an outbalance of HCS or N/PBTI will be examined. Finally, this chapter will evaluate if a general trend for a dominating MOSFET degradation mechanism is observable.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren
Vorheriges Kapitel Hot-Carrier Injection Degradation in Advanced CMOS Nodes: A Bottom-Up Approach to Circuit and System Reliability
Nächstes Kapitel Reliability Simulation Models for Hot Carrier Degradation
Literatur
1.
E. Takeda, N. Suzuki, An empirical model for device degradation due to hot-carrier injection. Electron Device Lett. 4(4), 111–113 (1983)CrossRef
2.
C. Hu et al., Hot-electron induced MOSFET degradation-model, monitor, improvement. IEEE Trans. Electron Devices ED-32, 375–385 (1985). IEEE Journal Solid-State Circuits, SC-20, 295–305 (1985)
3.
M. Brox et al., A model for the time- and bias-dependence of p-MOSFET degradation. IEEE Trans. Electron Devices 41(7), 1184–1196 (1994)CrossRef
4.
S.E. Rauch et al., High-V GS PFET DC hot-carrier mechanism and its relation to AC degradation. IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Reliab. 10(1), 40–46 (2010)CrossRef
5.
K.G. Anil et al., Electron–electron interaction signature peak in the substrate current versus gate voltage characteristics of n-channel silicon MOSFETs. IEEE Trans. Electron Devices 49(7), 1283–1288 (2002)CrossRef
6.
B. Fischer et al., Bias and temperature dependence of homogeneous hot-electron injection from silicon into silicon dioxide at low voltages. IEEE Trans. Electron Devices 44(2), 288–296 (1997)CrossRef
7.
C. Guerin, V. Huard, A. Bravaix, General framework about defect creation at the Si/SiO2 interface. J. Appl. Phys. 105(11), 114513-1–114513-12 (2009)CrossRef
8.
C. Schlünder et al., Trapping mechanisms in negative bias temperature stressed p-MOSFETs. Microelectron. Reliab. 39, 821–826 (1999)CrossRef
9.
H. Reisinger, O. Blank, W. Heinrigs, A. Muhlhoff, W. Gustin, C. Schlünder, Analysis of NBTI degradation- and recovery-behavior based on ultra-fast VT-measurements, in Proceedings International Reliability Physics Symposium (IRPS) (2006), pp.448–453
10.
T. Grasser, et al., The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability, in Proceedings International Reliability Physics Symposium (IRPS) (2010), pp.16–25
11.
D. Heh, C.D. Young, G. Bersuker, Experimental evidence of the fast and slow charge trapping/detrapping processes in high-K dielectrics subjected to PBTI stress. IEEE Electron Device Lett. 29(2), 180–182 (2008)CrossRef
12.
J. Shimokawa, M. Sato, C. Suzuki, M. Nakamura, Y. Ohji, Theoretical approach and precise description of PBTI in high-K gate dielectrics based on electron trap in pre-existing and stress-induced defects, in Proceedings IEEE International Reliability Physics Symposium (IRPS) (2009), pp.973–976
13.
K. Hofmann, et al., Highly accurate product-level aging monitoring in 40nm CMOS, in Symposium on VLSI Technology Digest of Technical Papers (VLSI), June 15–18, Honolulu, HI (2010), pp.27–28
14.
J. Keane et al., An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB. IEEE J. Solid State Circuits 45(4), 817–829 (2010)MathSciNetCrossRef
15.
D. Lorenz, G. Georgakos, U. Schlichtmann, Aging analysis of circuit timing considering NBTI and HCI, in Proceedings IEEE International On-Line Testing Symposium (IOLTS) (2009), pp. 3–8
16.
K.K. Kim, On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits. IEEE Trans. Circuits Syst. 57(10), 798–802 (2010)CrossRef
17.
R. Thewes, K. Goser, W. Weber, Characterization and model of the hot-carrier-induced offset voltage of analog CMOS differential stages, in Technical Digest, Electron Device Meeting (IEDM) (1994), pp.303–306
18.
19.
F.S. Lai, Y.F. Lin, A. Weng, K. Hsueh, F.L. Hsueh, Digitally-assisted analog designs for submicron CMOS technology, in International Symposium on VLSI Design Automation and Test (VLSI-DAT) (2010), pp.49–52
20.
B. Murmann, B. Boser, Digitally assisted analog circuits. Queue – DSPs 2(1), 64 (2004)CrossRef
21.
V. Reddy, et al., Impact of negative bias temperature instability on digital circuit reliability, in Proceedings International Reliability Physics Symposium (IRPS) (2002), pp.248–254
22.
E. Seevinck, F. List, J. Lohstroh, Static noise margin analysis of MOS SRAM cells. IEEE J. Solid State Circuits 22(5), 525–536 (1987)CrossRef
23.
L. Chang, D.M. Fried, J. Hergenrother, et al., Stable SRAM cell design for the 32nm node and beyond, in Digest of Technical Papers, Symposium on VLSI Technology (VLSI) (2005), pp.128–129
24.
G. LaRosa, W.L. Ng, S. Rauch, R. Wong, J. Sudijono, Impact of NBTI induced statistical variation to SRAM cell stability, in IEEE International Reliability Physics Symposium (IRPS), Proceedings 26–30 March (2006), pp.274–282
25.
A. Haggag, M. Moosa, N. Liu, et al., Realistic projections of product fails from NBTI and TDDB, in IEEE International Reliability Physics Symposium (IRPS) Proceedings (2006), pp.541–544
26.
T. Fischer, E. Amirante, K. Hofmann, M. Ostermayr, P. Huber, D. Schmitt-Landsiedel, A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors, in Proceedings European Solid-State Device Research Conference (ESSDERC) (2008), pp.51–54
27.
S. Drapatz, T. Fischer, K. Hofmann, E. Amirante, P. Huber, M. Ostermayr, G. Georgakos, D. Schmitt-Landsiedel, Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation, in Proceedings of European Solid State Device Research Conference (ESSDERC) (2009), pp.93–96
28.
C. Schlünder, S. Aresu, G. Georgakos, W. Kanert, H. Reisinger, K. Hofmann, W. Gustin, HCI vs. BTI?—Neither one’s out, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS) (2012), pp.2F. 4.1–2F. 4.6
29.
G.A. Rott, H. Nielen, H. Reisinger, W. Gustin, S. Tyaginov, T. Grasser, Drift compensating effect during hot-carrier degradation of 130nm technology dual gate oxide P-channel transistors, in Final Report IEEE Integrated Reliability Workshop (IIRW) (2013), pp.73–77
30.
M. Clinton, Variation-tolerant SRAM design techniques, Circuits Short Course Program, VLSI (2007)
31.
R. Thewes, R. Brederlow, C. Schlünder, P. Wieczorek, B. Ankele, A. Hesener, J. Holz, S. Kessel, W. Weber, Evaluation of MOSFET reliability in analog applications, in Proceedings of the European Solid-State Device Research Conference (ESSDERC) (2001), pp.73–80
32.
C. Schlünder, R. Brederlow, B. Ankele, W. Gustin, K. Goser, R. Thewes, Effects of inhomogeneous negative bias temperature stress on p-channel MOSFETs of analog and RF circuits. J. Microelectron. Reliab. 45, 39–45 (2005)CrossRef
33.
J.E. Chung, K.N. Quader, C.G. Sodini, P.-K. Ko, C. Hu, The effects of hot-electron degradation on analog MOSFET performance, in IEEE International Electron Devices Meeting (IEDM), Technical Digest, 9–12 December (1990), pp.553–556
34.
C. Schlünder, R. Brederlow, B. Ankele, A. Lill, K. Goser, R. Thewes, On the degradation of P-MOSFETs in analog and RF circuits under inhomogenous negative bias temperature stress, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS) (2003), pp.5–10
35.
R. Thewes, R. Brederlow, C. Schlünder, P. Wieczorek, A. Hesener, B. Ankele, P. Klein, S. Kessel, W. Weber, Device reliability in analog CMOS applications, in IEEE International Electron Devices Meeting (IEDM), Technical Digest (1999), pp.81–84
36.
V.-H. Chung, J.E. Chung, The impact of NMOSFET hot-carrier degradation on CMOS analog subcircuit performance. IEEE J. Solid State Circuits 30(6), 644–649 (1995)CrossRef
37.
R. Thewes, K.F. Goser, W. Weber, Hot carrier induced degradation of CMOS current mirrors and current sources, in Technical Digest IEEE International Electron Devices Meeting (IEDM) (1996), pp.885–888
38.
R. Thewes, M. Brox, K.F. Goser, W. Weber, Hot-carrier degradation of p-MOSFETs under analog operation. IEEE Trans. Electron Devices 44(4), 607–617 (1997)CrossRef
39.
R. Thewes, R. Brederlow, C. Schlünder, et al., MOS transistor reliability under analog operation, in Proceedings of the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) (2000), pp.1545–1554
40.
C. Schlünder, et al., On the PBTI degradation of pMOSFETs and its impact on IC lifetime, in International Integrated Reliability Workshop, Final Report (2011), pp.7–11
41.
M. Tiebout, Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS. IEEE J. Solid State Circuits 36(7), 1018–1024 (2001)CrossRef
42.
R. Brederlow, W. Weber, D. Schmitt-Landsiedel, R. Thewes, Hot carrier degradation of the low frequency noise of MOS transistors under analog operating conditions, in Proceedings International Reliability Physics Symposium (IRPS) (1999), pp.239–242
43.
S. Aresu, et al., Hot-carrier and recovery effect on p-channel lateral DMOS transistors, in Final Report IEEE Integrated Reliability Workshop (2011), pp.77–81
44.
P. Moens et al., Hot carrier degradation phenomena in lateral and vertical DMOS transistors. IEEE TED 51, 623–628 (2010)CrossRef
45.
S. Reggiani, S. Poli, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, S. Pendharkar, R. Wise, Physics-based analytical model for HCS degradation in STI-LDMOS transistors. IEEE Trans. Electron Devices 58(9), 3072–3080 (2011)CrossRef
46.
J.P. Campbell, P.M. Lenahan, A.T. Krishnan, S. Krishnan, NBTI: an atomic-scale defect perspective, in Proceedings Reliability Physics Symposium (2006), pp.442–447
47.
D. Varghese et al., OFF-state degradation in drain-extended NMOS transistors: interface damage and correlation to dielectric breakdown. IEEE Trans. Electron Devices 54(10), 2669–2678 (2007)CrossRef
48.
D.S. Ang, Z.Q. Teo, T.J.J. Ho, C.M. Ng, Reassessing the mechanisms of negative-bias temperature instability by repetitive stress/relaxation experiments. IEEE Trans. Device Mater. Reliab. 11(1), 19–34 (2011)CrossRef
49.
M. Toledano-Luque, B. Kaczer, T. Grasser, P. Roussel, J. Franco, G. Groeseneken, Toward a streamlined projection of small device BTI lifetime distributions. J. Vac. Sci. Technol. B 31(1), 01A114.1–01A114.4 (2013)
50.
I.C. Chen, J.Y. Choi, T.Y. Chan, T.C. Ong, C. Hu, The effect of channel hot-carrier stressing on gate oxide integrity in MOSFET, in Proceedings of the IEEE International Reliability Physics Symposium (1988), pp.1–7
51.
L. Labate, S. Manzini, R. Roggero, Hot-hole-induced dielectric breakdown in LDMOS transistors. IEEE Trans. Electron Devices 50(2), 372–377 (2003)CrossRef
52.
B. Kaczer, F. Crupi, R. Degraeve, P. Roussel, C. Ciofi, G. Groeseneken, Observation of hot-carrier-induced nFET gate-oxide breakdown in dynamically stressed CMOS circuits, in International Electron Devices Meeting (2002), pp.171–174
53.
F. Crupi, B. Kaczer, G. Groeseneken, A. De Keersgieter, New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs. IEEE Electron Device Lett. 24(4), 278–280 (2003)CrossRef
54.
S. Rangan, et al., Universal recovery behavior of negative bias temperature instability, in IEDM (2003), p. 341
55.
S. Ogawa et al., Interface-trap generation at ultrathin SiO2 (4–6nm)-Si interfaces during negative-bias temperature aging. J. App. Phys. 77(3), 1137 (1995)CrossRef
56.
V. Huard et al., NBTI degradation: from physical mechanisms to modelling. Microelectron. Reliab. 46, 1–23 (2006)CrossRef
57.
H. Reisinger et al., The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress, in Proceedings of the IRPS (2010), pp.7–15
58.
H. Reisinger, T. Grasser, C. Schlünder, A study of NBTI by the statistical analysis of the properties of individual defects in pMOSFETs, in Final Report. International Integrated Reliability Workshop (IRW) (2009), pp.30–35
59.
T. Grasser et al., Time-dependent defect spectroscopy for characterization of border traps in metal-oxide-semiconductor transistors. Phys. Rev. B 82(24), 5318–5327 (2010)CrossRef
60.
T. Aichinger, et al., Unambiguous identification of the NBTI recovery mechanism using ultra-fast temperature changes, in Proceedings of the IRPS (2009), pp.2–7
61.
P. Moens, G. Van den Bosch, Characterization of total safe operating area of lateral DMOS transistors. IEEE Trans. Electron Devices. 6, 340–357 (2006)
Metadaten
Titel
Circuit Reliability: Hot-Carrier Stress of MOS Transistors in Different Fields of Application
verfasst von
Christian Schlünder
Copyright-Jahr
2015
Buch
Hot Carrier Degradation in Semiconductor Devices

Print ISBN: 978-3-319-08993-5

Electronic ISBN: 978-3-319-08994-2

Copyright-Jahr: 2015

DOI
https://doi.org/10.1007/978-3-319-08994-2_15

Neuer Inhalt

    Bildnachweise