5. Circuit Solutions

CMOS technologies move steadily towards finer geometries, which provide higher digital capacity, lower dynamic power consumption and smaller area resulting in integration of whole systems, or large parts of systems, on the same chip. However, due to technology scaling, integrated circuits are becoming more susceptible to variations in process parameters and noise effects like power supply noise, cross-talk reduced supply voltage and threshold voltage operation severely impacting the yield [1]. Since parameter variations depend on unforeseen operational conditions, chips may fail despite they pass standard test procedures. Similarly, the magnitude of thermal gradients and associated thermo-mechanical stress increase further as CMOS designs move into nanometer processes and multi-GHz frequencies [1]. Higher temperature increases the risk of damaging the devices and interconnects since major back-end and front-end reliability issues including electro-migration, time-dependent dielectric breakdown, and negative-bias temperature instability have strong dependence on temperature. As a consequence, continuous observation of process variation and thermal monitoring becomes necessity. Such observation is enhanced with dedicated monitors embedded within the functional cores [2]. In order to maximize the coverage, the process variation and thermal sensing devices are scattered across the entire chip to meet the control requirements. The monitors are networked by an underlying infrastructure, which provides the bias currents to the sensing devices, collects measurements, and performs analog to digital signal conversion. Therefore, the supporting infrastructure is an on-chip element at a global scale, growing in complexity with each emerging design.