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Erschienen in:
Signal Processing Methods for Light Field Displays Kapitel lesen Erstes Kapitel lesen

2019 | OriginalPaper | Buchkapitel

Coarse-Grained Reconfigurable Array Architectures

verfasst von : Bjorn De Sutter, Praveen Raghavan, Andy Lambrechts

Erschienen in: Handbook of Signal Processing Systems

Verlag: Springer International Publishing

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Abstract

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high instruction-level parallelism (ILP) support in very long instruction word (VLIW) architectures. Unlike VLIWs, CGRAs are designed to execute only the loops, which they can hence do more efficiently. This chapter discusses the basic principles of CGRAs and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support, and for the manual fine-tuning of source code.

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Vorheriges Kapitel Arithmetic
Nächstes Kapitel High Performance Stream Processing on FPGA
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Metadaten
Titel
Coarse-Grained Reconfigurable Array Architectures
verfasst von
Bjorn De Sutter
Praveen Raghavan
Andy Lambrechts
Copyright-Jahr
2019
Buch
Handbook of Signal Processing Systems

Print ISBN: 978-3-319-91733-7

Electronic ISBN: 978-3-319-91734-4

Copyright-Jahr: 2019

DOI
https://doi.org/10.1007/978-3-319-91734-4_12

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