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2000 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

Code Optimization Techniques for Embedded Processors

Methods, Algorithms, and Tools

verfasst von: Dr. Rainer Leupers

Verlag: Springer US

Enthalten in: Professional Book Archive

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Über dieses Buch

The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Traditionally, these embedded processors mostly have been pro­ grammed in assembly languages due to efficiency reasons. This implies time­ consuming programming, extensive debugging, and low code portability. The requirements of short time-to-market and dependability of embedded systems are obviously much better met by using high-level language (e.g. C) compil­ ers instead of assembly. However, the use of C compilers frequently incurs a code quality overhead as compared to manually written assembly programs. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice. In turn, this requires new compiler techniques that take the specific constraints in embedded system de­ sign into account. An example are the specialized architectures of recent DSP and multimedia processors, which are not yet sufficiently exploited by existing compilers.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
According to the 1998 SIA roadmap [SIA98], integrated circuits (ICs) at the end of this decade will typically have more than 500 million transistors, an integration scale more than one order of magnitude higher than in today’s microelectronics. For the high performance processor segment, even larger integration scales have been predicted, with processor performance reaching 3 million MIPS by the year 2010 [Tech00].
Rainer Leupers
Chapter 2. Memory Address Computation for DSPs
Abstract
In this chapter, we describe two code optimization techniques for DSPs, which exploit the special address generation hardware in such processors. These optimizations are very “low-level” in the compilation flow, because they demand that machine code, in the form of sequential assembly code with symbolic variables, has already been generated in earlier phases (fig. 2.1). One degree of freedom that can be exploited at this point is the way in which symbolic variables are laid out in memory and how the memory addresses of the variables are computed at program runtime.
Rainer Leupers
Chapter 3. Register Allocation for DSP Data Paths
Abstract
This chapter deals with the register allocation problem in DSP code generation. Since DSP data paths typically show special-purpose registers, register allocation for such architectures has to be performed carefully in order to achieve high code quality. In particular, this holds if code is generated for data flow graphs, which are a widespread internal representation of program blocks. Such data flow graphs are composed of data flow trees, for which satisfactory code generation techniques have already been developed. In the following, we will extend this work by an algorithm that allocates registers for common subexpressions in data flow graphs, which can be considered as the interfaces between the data flow trees in the graph.
Rainer Leupers
Chapter 4. Instruction Scheduling for Clustered VLIW Processors
Abstract
This chapter presents a code optimization technique for a special class of processor data paths, which we call clustered VLIW. Here, a cluster denotes a piece of the data path with functional units (FUs) and a local register file. Such a data path architecture is frequently found in multimedia processors and ASIPs. We will focus on the problem of instruction scheduling. Fig. 4.1 shows how this phase relates to the overall compilation flow.
Rainer Leupers
Chapter 5. Code Selection for Multimedia Processors
Abstract
In this chapter we consider the problem of mapping a machine-independent intermediate representation into assembly code for multimedia processors. Fig. 5.1 shows the position of this code selection problem in the compilation flow.
Rainer Leupers
Chapter 6. Performance Optimization with Conditional Instructions
Abstract
The techniques presented in the previous chapters are strongly machine-dependent, since they are based on knowledge of the detailed data path architectures of embedded processors. In contrast, this chapter describes a largely machine-independent code optimization technique, which primarily works on the intermediate representation (IR) level of the compilation flow (fig. 6.1).
Rainer Leupers
Chapter 7. Function Inlining under Code Size Constraints
Abstract
In this chapter we consider a performance optimization technique working at the source code level (fig. 7.1). This technique is based on function inlining, which is a well-known concept in compiler construction. Function inlining eliminates function call overhead by replacing function calls with copies of function bodies. While this optimization generally results in higher performance, it also increases the code size.
Rainer Leupers
Chapter 8. Frontend Issues — The LANCE System
Abstract
The code optimization techniques presented in the previous chapters mainly refer to what is commonly called the backend of a compiler, i.e., the machine dependent part responsible for assembly code generation. However, a significant portion of the total design effort for writing a compiler also goes into the machine-independent parts, i.e., the frontend. This includes the source language parser, as well as machine independent optimizations working on the intermediate representation (IR). In most cases, a frontend is required for experimentally evaluating new code generation techniques. Also the transfer of research results into industrial practice can hardly be accomplished without a frontend.
Rainer Leupers
Chapter 9. Conclusions
Abstract
The need for higher productivity in embedded system design demands for taking the step from assembly to C level programming of embedded processors. While compiler technology is relatively mature for general-purpose processors, this generally is not the case for embedded processors. The reason is that embedded systems require higher code efficiency than general-purpose systems. Simultaneously, recent embedded processors show specialized architectural features that cannot be well exploited with standard compiler techniques. However, C compilers for embedded processors will only gain more acceptance in industry, if their code quality overhead is low as compared to assembly code. The key concept to overcome these problems is the development of new compiler techniques that take the special constraints in embedded system design into account.
Rainer Leupers
Backmatter
Metadaten
Titel
Code Optimization Techniques for Embedded Processors
verfasst von
Dr. Rainer Leupers
Copyright-Jahr
2000
Verlag
Springer US
Electronic ISBN
978-1-4757-3169-9
Print ISBN
978-1-4419-5010-9
DOI
https://doi.org/10.1007/978-1-4757-3169-9