Compilers and Operating Systems for Low Power

Operating systems in embedded wireless communication increasingly must satisfy a tight set of constraints, such as power and real time performance, on heterogeneous software and hardware architectures. In this domain, it is well understood that traditional general-purpose operating systems are not efficient or in many cases not sufficient. More efficient solutions are obtained with OS's that are developed to exploit the reactive event-driven nature of the domain and have built-in aggressive power management. As proof, we present a comparison between two OS's that target this embedded domain: one that is general-purpose multi-tasking and another that is event-driven. Preliminary results indicate that the event-driven OS achieves an 8x improvement in performance, 2x and 30x improvement in instruction and data memory requirement, and a 12x reduction in power over its general-purpose counterpart. To achieve further efficiency, we propose extensions to the event driven OS paradigm to support power management at the system behavior, system architecture, and architecture module level. The proposed novel hybrid approach to system power management combines distributed power control with global monitoring.

We present a modification of the dual-priority scheduling algorithm for hard real-time systems that takes advantage of its performance to efficiently improve energy saving. The approach exploits the priority scheme to lengthen the runtime of tasks by reducing the speed of the processor and the voltage supply, thereby saving energy by spreading execution cycles up to the maximal time constraints allowed. We show by simulation that our approach improves the energy saving obtained with a pre-emptive fixed-priority scheduling scheme.

In this chapter we present a methodology to analyze the energy overhead due to the presence of an embedded operating system in a wearable device. Our objective is to determine the key parameters affecting the energy consumption of the RTOS allowing the development of more efficient OS-based power management policies. To achieve this target, we present a characterization strategy that stimulates the RTOS both at the kernel and at the UO driver level by analyzing various OS-related parameters. Our analysis focus in particular on the relationship between energy consumption and processor frequency characterizing the different functionalities of an RTOS, suggesting a way to develop effective OS-aware energy optimization policies based on variable voltage and frequency. Experimental results are presented for eCos, an open-source embedded OS ported and installed on a prototype of wearable device, the HP SmartBadgeIV.¹

In this chapter we address power conservation for clusters of workstations or PCs. Our approach is to develop systems that dynamically turn cluster nodes on - to be able to handle the load imposed on the system efficiently - and off - to save power under lighter load. The key component of our systems is an algorithm that makes cluster reconfiguration decisions by considering the total load imposed on the system and the power and performance implications of changing the current configuration. The algorithm is implemented in two common cluster-based systems: a network server and an operating system for clustered cycle servers. Our experimental results are very favorable, showing that our systems conserve both power and energy in comparison to traditional systems.

In a pervasive computing environment, applications are able to run across different platforms with significantly different resources. Such platforms range from high-performance desktops to handheld PDAs. This chapter discusses a compiler approach to reduce the energy consumption of a diskless device where the swap space is provided by a remotely mounted file system accessible via a wireless connection. Predicting swapping events at compile time allows effective energy management of a PDA's wireless communication component such as a 802.11 or Bluetooth card.

The compiler activates and de-activates the communication card based on compile-time knowledge of the past and future memory footprint of an application. In contrast to OS techniques, the compiler can better predict future program behavior, and can change this behavior through program transformations that enable additional optimizations.

A prototype compilation system EEL_RM has been implemented as part of the SUIF2 compiler infrastructure. Preliminary experiments based on the SimpleScalar simulation toolset and three numerical programs indicate the potential benefits of the new technique.

Many embedded systems include a microprocessor that executes a single program for the lifetime of the system. These programs often contain constants used to initialize control registers in peripheral hardware components. Now that peripherals are often purchased in intellectual property (core) form and synthesized along with the microprocessor onto a single chip, new optimization opportunities exist. We introduce one such optimization, which involves propagating the initialization constants past the microprocessor to the peripheral, such that synthesis can further propagate the constants inside the peripheral core. While constant propagation in synthesis tools is commonly done, this work illustrates the benefits of recognizing initialization constants from the software as really being constants for hardware. We describe results that demonstrate 2–3 times reductions in peripheral size, and 10–30% savings in power, on several common peripheral examples.

In this chapter, we first present a cycle-accurate power simulator based on the IMPACT toolset. This simulator allows a designer to evaluate both VLIW compiler and micro-architecture innovations for power reduction. Using this simulator, we then develop and compare the following techniques with a bounded performance loss of 1% compared to the case without any dynamic throttling: (i) clock ramping with hardware-based prescan (CRHP), and (ii) clock ramping with compiler-based prediction (CROP). Experiments using SPEC2000 floating point benchmarks show that the power consumed by floating point units can be reduced by up to 31% and 37%, in CRHP and CROP respectively.

Turbo coding has become an attractive scheme for design of current communication systems, providing near optimal bit error rates for data transmission at low signal to noise ratios. However, it is as yet unsuitable for use in high data rate mobile systems owing to the high energy consumption of the decoder scheme. Due to the data dominated nature of the decoder, a memory organization providing sufficient bandwidth is the main bottleneck for energy. We have systematically optimized the memory organization’s energy consumption using our Data Transfer and Storage Exploration methodology. This chapter discusses the exploration of the energy versus throughput trade-off for the turbo decoder module, which was obtained using our storage bandwidth optimization tool.

Caches are an important part of architectural and compiler low-power strategies by reducing memory accesses and energy per access. In this chapter, we examine efficient utilization of data caches for low power in an adaptive memory hierarchy. We focus on the optimization of data reuse through the static analysis of line size adaptivity. We present an approach that enables the quantification of data misses with respect to cache line size at compile-time. This analysis is implemented in a software package STAMINA. Experimental results demonstrate effectiveness and accuracy of the analytical results compared to alternative simulation based methods.

We challenge the apparent consensus that next-generation mobile devices must necessarily provide resource-intensive capabilities such as on-device Java implementations to support advanced applications. Instead, we propose an architecture that exploits the high “last mile” bandwidth in third generation wireless networks to enable the largest part of such applications to run inside a base station, effectively reducing the mobile device to a dumb terminal. We discuss some implications of this architecture, with respect to hand-off, confidentiality while roaming in potentially hostile networks, and the need for a server-transparent segmentation of applications into a computational and a user interface component.