Depth optimization for topological quantum circuits

Topological quantum computing (TQC) model is one of the most promising models for quantum computation. A circuit implemented under TQC is optimized by reducing its depth due to special construction requirements in such technology. In this work, we propose a hybrid approach that combines a left-edge greedy heuristic with genetic algorithm (GA) to minimize circuit depth through combined line and gate ordering. In our implementation, GA is used to find line ordering, whereas the left edge is used to reduce circuit depth by taking into consideration overlap constraints imposed by line ordering. Moreover, the proposed algorithm can merge gates together realizing circuit with multi-target gates to provide reduced circuit depth. Experimental results on random benchmark circuits show that the proposed algorithm was able to reduce circuit depth by 42 % on average for CNOT circuits, with additional 5 % savings when multi-target optimization is used. Results on RevLib benchmarks revealed a typical enhancement of 21 % and an additional 11 % when multi-target gates are allowed.