Design of 8-Bit Programmable Crossbar Switch for Network-on-Chip Router

The Network-on-Chip (NoC) uses multiple processors, usually targeted for embedded applications. This is widely accepted that NoC represents a promising solution for forthcoming complex embedded systems. The current SoC Solutions are built from heterogeneous hardware and Software components integrated around a complex communication infrastructure. The crossbar is a vital component of in any NoC router. The crossbar allocates requested output channel. Hence, switches must include an efficient arbiter that allocates crossbar’s resources(channel). In this paper, we present a novel 8-bit wide 8 x 8 crossbar that is implemented on FPGA. This high performance crossbar is coined with Diagonal Propagation Arbiter (DPA). The presented crossbar requires a two-dimensional arbitration that incorporates a diagonally rotated priority to provide fair arbitration. The arbiter is capable of performing arbitration in 1ns on Vertex 6 FPGA technology for an 8 x 8 crossbar. The proposed architecture of crossbar is implemented in RTL model using verilog language.