Design of a MEMS speaker driver

One of the biggest challenges for MEMS speaker drivers is the non-linear behavior of the speaker’s capacitance. Piezoelectric materials have a non-linear dielectric constant which results in a capacitance of the speaker that depends on the voltage as well as the displacement of the membrane. This behavior is already well known and for example described in [3, 4]. The results of these investigations can be used for a polynomial approximation of this behavior. A second order polynomial is used to model the capacitance as a function of the applied voltage where \(C_{\text{Speaker}}\) is the non-linear speaker capacitance, \(C_{\text{n}}\) is the nominal capacitance of the speaker, \(P_{ \text{i,n}}\) are the non-linear coefficients and \(V_{\text{DC}}\) is the DC voltage at the speaker. The difference between the measured non-linearity and the approximation can be seen inside Fig. 2 for a 1 V peak-to-peak AC signal and different DC offset voltages at 10 kHz. It can be seen that the slope is approximately constant and only drops at low DC offset voltages. To avoid that the polarity of the voltage across the piezoelectric material changes, the speaker requires a constant DC offset which will be set to the middle of the maximum required output voltage. To achieve 30 \(V_{PP}\) at the speaker, a minimum DC offset of 15 V is required.

It can be seen, that the non-linearity is not only depending on the DC voltage, but is also varying over the audio frequency range. Figure 3 shows this effect based on measurements results. Compared to the voltage depending non-linearity, this effect is considered to be small and won’t be considered for first driver designs.

The fact that a MEMS speakers present a capacitive load to the driver results in a difference in the power factor \(\cos(\phi)\) compared to conventional electrodynamic speakers. The power factor describes the ratio of real power \(P\) to apparent power \(S\) where \(\phi\) is the phase shift between the voltage and current. This factor can be in the range of \(0^{\circ}\) to \(45^{\circ}\) for electrodynamic or balanced armature speakers. This results in a considerable amount of real power which causes a temperature increase at the speaker. Compared to this value, the power factor for MEMS speakers is in the range of \(80^{\circ}\) to \(90^{\circ}\) which shows that the real power losses inside the speaker are very low compared to electrodynamic speakers. This results in a much lower temperature increase of the speaker which can be seen in Fig. 4. Compared to the electrodynamic speaker which reaches \(40.1~^{\circ}\mbox{C}\) at the membrane and \(50.9~^{\circ}\mbox{C}\) at the coil, the temperature of the MEMS speaker is with \(29.4~^{\circ}\mbox{C}\) only slightly higher than the desk on which they were placed.

A third important parameter of MEMS speakers is the hysteresis effect of the speaker. Figure 5 shows the hysteresis of the speaker as a function of the applied voltage and the resulting current into the speaker. This effect is dependent on the type of driving architecture used, as described in [5, 6] and is considered inside for the driving concept as well.

Class D amplifiers are very often used inside low power applications. To analyze the impact of the capacitive load on the amplifier, only the output stage will be considered. Figure 6 shows the block diagram of a typical Class D amplifier architecture.

A key parameter for mobile audio applications is the efficiency of the used amplifier. This is also a point where the biggest impact of the different load can be seen and new considerations have to be taken. The efficiency of audio amplifiers for electrodynamic speaker is often calculated based on the average power at the output [7]. where \(P_{\text{Average}}\) is the average active power, \(T\) the period of the signal, \(u_{\text{(t)}}\) the current value of the voltage, \(i_{\text{(t)}}\) the current value of the current, \(V_{\text{RMS}}\) the root mean square (RMS) value of the voltage and \(I_{\text{RMS}}\) the RMS value of the current. As shown above, the power factor for MEMS speakers is approaching zero which would result in a very low efficiency. For this reason the apparent power will be used to calculate the efficiency of amplifiers with capacitive loads [7]. where \(P_{\text{out}}\) is the apparent output power and \(P_{\text{diss}}\) the amplifier dissipation. The losses of the amplifier can be separated into following parts [7]: where \(P_{\text{Q}}\) is the quiescent power loss of the amplifier, \(P_{\text{CL}}\) the conduction losses of the output drivers, \(P_{\text{SW}}\) the switching losses, \(P_{\text{BD}}\) the bulk diode of the driving transistors and \(P_{\text{Filt}}\) the losses inside the output filter and load. Considering the four parts of the power losses [7] calculated in (6) to (10) where \(I_{\text{out,rms}}\) is the output RMS current, \(R_{ \text{ds,on}}\) is the drain source on resistance of the output transistor, \(F_{\text{SW}}\) the switching frequency, \(V_{\text{CP}} ^{2}\) the voltage at each parasitic capacitance at the output, \(C_{\text{P,i}}\) the parasitic capacitances at the output, \(V_{ \text{SD}}\) the body diode voltage drop, \(I_{\text{pk}}\) the peak output current, \(t_{\text{dt}}\) the dead time, \(I_{\text{rrm}}\) the body diode reverse recovery current, \(t_{\text{rr}}\) the reverse recovery time, \(|Z_{\text{L}}| \cdot\cos ( \varPhi ) \) the resistive part of the output filter, \(C_{\text{load}}\) the load capacitance and \(f\) the applied frequency at the output, two major drawbacks of a Class D amplifier together with capacitive loads for ultra low power applications can be seen. First the conduction losses and the body diode losses are related to the output current (either rms or peak). Especially at high frequencies this current will be considerable high which causes high losses inside the output switches.

Second, the size of the inductor can be a critical parameter, especially for a small load capacitance as it is the case for MEMS speakers. Considering a load of 100 nF and a cutoff frequency of 29 kHz would results in an inductor value of approximately 300 μH for the output filter.

Class H amplifiers are a good alternative compared to Class D amplifiers in low power applications. Figure 7 shows the block diagram for a typical Class H amplifier. This type of amplifier is basically a class AB architecture where the supply voltage of the output stage will be regulated based on the required output swing. The way the supply voltage is regulated is the main difference between a Class G and a Class H amplifier. Figure 8 shows both supply voltage regulation topologies. Compared to Class G amplifiers, the supply voltage follows the signal continuously for a Class H Amplifiers whereas there are discrete supply voltages levels inside Class G amplifiers.

The efficiency of Class H amplifiers will be typically calculated in two different operating areas. The first area is where the input signal is small so that the adaptive supply voltage regulation is not working. In this region the Class H amplifier works like an Class AB amplifier. For simplifications only this operating region will be analyzed for the efficiency calculations.

Considering a resistive load the maximum possible efficiency of a Class AB amplifier can be calculated as

Considering a capacitive load, the resulting maximum possible efficiency reduces to according to [8]. It can be seen that the efficiency will be dramatically reduced. Although power amplifiers with energy recovery functionality were proposed [9], they still require a charge pump which generates the high output voltage. Moreover, high voltage devices are required which increase the chip area and complexity of the design. Therefore, circuit architectures are required that work with a minimum number of high voltage devices and keep the chip area and the number of required external components at a minimum.

One of the most basic circuits for capacitive energy transfer is the switched capacitor voltage doubler [10]. The basic circuit diagram of a switched capacitor voltage doubler can be found in Fig. 9. Four stages are required to generate an input voltage to output voltage ratio of at least 10. The efficiency of the circuit is one of the most important parameters. For this reason the energy loss caused by connecting two capacitors in parallel is calculated.

Connecting two capacitors in parallel results in a common voltage \(V_{\text{common}}\) which can be calculated as where \(Q_{\text{ges}}\) is the total charge inside the system, \(C_{\text{1}}\) is the first capacitor, \(V_{\text{1}}\) the voltage at the first capacitor, \(C_{\text{2}}\) is the second capacitor and \(V_{\text{2}}\) the voltage at the second capacitor, which results in an energy \(E_{\text{common}}\) inside the system after charge transfer of

Based on this, the energy loss \(\Delta E\) during the charge transfer can be calculated. The initial energy \(E_{\text{0}}\) inside the system can be written as which results in an energy loss off

It can be seen that there is always an energy loss once charge is transferred from one capacitor to another. Assuming two identical capacitors this results in the fact that the output voltage will be half of the input voltage and output energy which is only a quarter of the input energy. This is a major drawback of a capacitive based solution. Nevertheless it is also important to notice that the energy loss is not depending on the switch on resistance.

The second major drawback of this solution will become obvious once charge recovery structures will be considered. In a typical voltage doubler or any charge pump circuit, the energy transfer goes from the input to the output of the voltage doubler. This is not the case if energy recovery will be considered. The basic block diagram of such an architecture is shown inside Fig. 10.

In such an architecture, the current inside the output stages (at least in the third and fourth stage) is bidirectional and can flow towards the load but also from the load towards the internal storage capacitor. This requires symmetrical high voltage switches inside these stages, which limits the number of available process technologies. Also the capacitors required for the voltage doublers can be in the range of up to 100 nF for the first stages (due to the high reactive power which is required at the output) which would require either a big silicon area or additional external components.

An alternative approach to the capacitor based solutions are inductor based architectures. The first applications for such architectures were plasma panels where the fundamentals of inductor based charge recovery were developed and patented [11]. The basic structure of such an energy recovery system can be seen in Fig. 11.

These architectures work on the principle where energy will be transferred either from the supply or a storage capacitor to the load (typically a capacitor or device with capacitive behavior) using an inductor.

Nowadays these types of architectures are again becoming important especially for applications like piezoelectric actuators where also high voltages are required and the load can be considered as a capacitive load [13]. Figure 12 shows such a circuit which is used to drive a piezoelectric actuator.

Most of the circuits which include energy recovery as well are used to generate rectangular output signals. These types of applications are working typically with very high voltages and the requirements on the signal quality are usually lower.

One disadvantage of all previously discussed architectures is the fact that they need a separate boost converter to generate the high output voltage at the driver stage, where also the generation of the additional required DC offset has to be considered. New solutions should be aimed at the development of new driver architectures, that combine the amplifier and the boost converter stage in an efficient way and to use energy recovery concepts without having a significant impact on the signal quality.

Based on solutions for the generation of rectangular output signals, the transition to high quality audio signals with low THD has to be made. Because of the high output voltage, also large signal parameters like the slew rate have to be observed.

The voltage at the load can be expressed as where \(v_{\text{load}}\) is the voltage at the speaker, \(V_{\text{DC}}\) is the DC voltage at the speaker, \(V_{\text{P}}\) is the peak AC voltage at the speaker and \(f_{\text{max}}\) the maximum possible output signal frequency. This results in a required slew rate of which is for an audio frequency up to 20 kHz with maximum amplitudes of 30 V peak to peak in the range of 1.885 V/μs. This high slew rate is also the reason why currently available audio amplifiers for ceramic speakers are limiting the output voltage swing for frequencies higher than approximately 10 kHz.

Figure 13 shows the basic block diagram of the proposed solution.

The core of the circuit is the HV driver stage which is similar to the one shown inside Fig. 12. The advantage of this architecture is the fact that no additional boost converter is required and the high output voltage is directly generated at the load. Therefore, with small modifications on the output stage, only two devices have to be high voltage devices.

Since the high voltage is generated directly at the load, this node is very sensitive related to currents drawn from the load. Therefore special considerations have to be taken into account to design the voltage divider, which is required to keep the voltage of the ADC input stage in the allowed range for low voltage devices.

Another important design aspect is the switching of the output driver. This has to be done in a way to keep on one side the output transistors on resistance as low as possible and on the other hand to avoid any unwanted oscillation on the output which would decrease the system efficiency.

To be able to generate a sine wave output signal, a feedback loop is introduced including a voltage divider and analog to digital converter. This feedback provides the information for the digital controller to be able to drive the boost energy-recovery stage and at the same time eliminating non-linear effects from the speaker.

To be able to control the HV stage, an accurate PWM signal is required to control the driver switches. Based on this PWM signal, the voltage steps at the output of the amplifier can be controlled which allows an accurate control of the output voltage and therefore an increased signal quality. The control of the system should also be able to support the high dynamic range of the audio signals. A human ear has a dynamic range of 130 dB which should be considered during the design of the control loop. Therefore a trade off between speed (required for high frequency signals with high amplitude) and signal quality at lower amplitudes has to be found.

The simulations were done based on a MATLAB/Simulink model of the whole system including non linear effects of the speaker. Figure 14 shows the first results based on a 5 kHz input signal. A total harmonic distortion of \(-78~\mbox{dB}\) and a SNR of 86 dB could be achieved at 15 Vp output amplitude.

Also the energy recovery efficiency was analyzed using simulations. The energy consumed by the amplifier could be reduced by 67% including energy recovery compared to the same driving circuit but without energy recovery.

The first measurement results based on an HV driver fabricated in a 0.18 μm XFAB SOI HV process and FPGA for the control loop. The results of the measurement can be seen in Fig. 15.

The currently maximum achievable SNR based on measurements is approximately 60 dB. The low SNR is mainly related to the used analog circuitry on the PCB to divide the high output voltage to a lower level for the ADC input. This currently limits the overall accuracy of the ADC to approx. 8 bit and needs to be improved.