Design of CMOS Analog Integrated Fractional-Order Circuits

Fractional calculus is three centuries old as the conventional calculus and consist a super set of integer-order calculus, which has the potential to accomplish what integer-order calculus cannot. Its origins dating back to a correspondence from 1695 between Leibnitz and L’Hôpital, with L’Hôpital inquiring about Leibnitz notation for the n-th derivative of a function d ⁿ y/dx ⁿ , i.e. what would be the result if n = 1/2. The reply from Leibnitz, “It will lead to a paradox, a paradox from which one day useful consequences will be drawn, because there are no useless paradoxes”, was the motivation for fractional calculus to be born. Fractional calculus does not mean the calculus of fractions, nor does it mean a fraction of any calculus differentiation, integration or calculus of variations. The fractional calculus is a name of theory of integrations and derivatives of arbitrary order, which unify and generalize the notation of integer-order differentiation and n-fold integration. The beauty of this subject is that fractional derivatives and integrals translate better the reality of nature! This feature turns it into an efficient tool, offering the capability of having available a language of nature, which can be used to talk with.

This chapter presents a systematic procedure for designing fractional-order transfer functions. Fractional-order differentiator, lossless and lossy integrator of order α, and fractional-order filters of any type (i.e., low-pass, high-pass, band-pass, band-stop) of order 1 + α, α + β, and n + α, where n is the integer-order and corresponds to values n ≥ 2, and α is the order of the fractional part (0 < α < 1), are realized by the same core, and therefore this is very important from the flexibility point of view. Functional block diagrams in case of using a voltage-mode or a current - mode technique are presented, while the second-order of CFE is utilized in order to approximate the variable s ^α .

This chapter presents a current-mode technique for realizing fractional-order filters, where low-voltage current mirrors are employed as active elements. A novel topology of a current mirror, which is able to realize large time-constants is introduced. The proposed topology is then used for realizing transfer functions of fractional-order differentiator, lossless and lossy integrator of order α, and fractional-order filters of any type (i.e., FLPF, FHPF, FBPF, FBSF) of order 1 + α, which are realized by the same core, and therefore, they can be considered as generalized filter structures. The performance of the aforementioned circuits has been evaluated using the Analog Design Environment of the Cadence software and the Design kit provided by the TSMC 180 nm CMOS process.

This chapter presents a voltage-mode technique for realizing fractional-order filters. Low-voltage OTAs are employed as active elements. Fractional-order filters are designed with the additional benefit that different types of filter functions are realized using the same topology. As a result, the resulted filter functions are generalized. Firstly, fractional order lowpass, highpass, allpass, and bandpass filters of order α are realized the efficiency of which is verified through simulations results. In addition, fractional order lowpass, highpass, bandpass, and bandstop filters of order α + β are also given. Both designs employed MOS transistors biased in subthreshold region, offering also the benefit of low voltage operation. The design of these topologies is realized using the AMS 0.35 μm CMOS technology.

The design of fractional-order capacitors and inductor emulators is introduced in a systematic way procedure, where the second-order approximation of the CFE is utilized in order to approximate the variable s ^α of fractional calculus. OTAs are employed as building blocks, using MOS transistors biased in subthreshold region, offering the advantage of operating in a low voltage environment. The emulation schemes that have been proposed are voltage excited, as well as current excited in order to be available for different types of applications based on potentiostatic and galvanostatic measurements, respectively. Both emulators (capacitor and inductor) are fabricated in AMS 0.35 μm CMOS technology, the efficiency of which is verified through experimental results. As a design example, a fractional-order resonator is presented.

This chapter focuses on the design of novel topologies that are suitable for implementing fractional-order circuits, which offer attractive features, especially when they are applied in biomedical applications. The design examples that will be presented are (i) the efficiency of fractional-order differentiators for handling signals in a noisy environment using the Pan-Tompkins algorithm, (ii) a fully tunable implementation of a biological tissue using fractional-order capacitors, (iii) a simple non-impedancebased measuring technique for supercapacitors, and (iv) the design and evaluation of a fractional-order oscillator. Then main feature that has been proved is the fact that fractional-order circuits offer better performance when compared to their integer-order counterparts. In case of designing the fractional-order differentiator for being used in the Pan-Tompkins algorithm, the Sinh-Domain technique (companding filtering) has been employed, while the nonlinear transconductances that have been used as active elements were build using MOS transistors biased in subthreshold region, offering also the benefit of low- voltage operation. In addition, fractional-order capacitors are designed using OTAs as active elements, offering also the benefit of low- voltage operation. The behaviour of the proposed structures is evaluated through simulation results.

Throughout this work the second-order approximation of the CFE is utilized in order to present a systematic way for describing the design equations of fractional-order generalized transfer functions. Thus, fractional-order transfer functions are approximated using integer-order transfer functions, which are easy to realize. The main active cells that are employed are current mirrors, nonlinear transconductance cells (known as S, C cells), and OTAs, which are very attractive building blocks offering the capability of implementing resistorless realizations with electronic tuning, where only grounded capacitors are employed. As a result, the designer has only to choose the appropriate values of DC bias currents in order to realize the desired transfer function. Taking into account that MOS transistors are biased in subthreshold region, these topologies are able to operate in a low-voltage environment with reduced power consumption, making them attractive candidates for realizing fractional-order circuits in various interdisciplinary applications.