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2011 | Buch

1 Digital System Design Kapitel lesen Erstes Kapitel lesen

Design of Digital Systems and Devices

herausgegeben von: Marian Adamski, Alexander Barkalov, Marek Węgrzyn

Verlag: Springer Berlin Heidelberg

Buchreihe : Lecture Notes in Electrical Engineering

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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Über dieses Buch

Logic design of digital devices is a very important part of the Computer Science. It deals with design and testing of logic circuits for both data-path and control unit of a digital system. Design methods depend strongly on logic elements using for implementation of logic circuits. Different programmable logic devices are wide used for implementation of logic circuits. Nowadays, we witness the rapid growth of new and new chips, but there is a strong lack of new design methods.

This book includes a variety of design and test methods targeted on different digital devices. It covers methods of digital system design, the development of theoretical base for construction and designing of the PLD–based devices, application of UML for digital design. A considerable part of the book is devoted to design methods oriented on implementing control units using FPGA and CPLD chips. Such important issues as design of reliable FSMs, automatic design of concurrent logic controllers, the models and methods for creating infrastructure IP services for the SoCs are also presented.

The editors of the book hope that it will be interesting and useful for experts in Computer Science and Electronics, as well as for students, who are viewed as designers of future digital devices and systems.

Inhaltsverzeichnis

Frontmatter

System Design

Frontmatter
1 Digital System Design
Abstract
The most complicated stage of each design, namely the system design, is discussed. An example of the design for a rather simple processor is shown. A design procedure is proposed, which included such steps as combination of separate algorithmic state machines (ASM); synthesis of data-path; control unit design, and composition of data-path and control unit into whole processor. The main advantage of proposed procedure is formalization of the design process, where all steps are formalized and automated in EDA tool “Abelite” designed by the author of this chapter.
Samary Baranov
2 Rectangular Function Π(x) and Its Application for Description of Some Logical Devices Operation
Abstract
A carrying out of the logic operations on pulses and pulse series described by means of rectangular function Π(x) is presented in the section. The logic sum, logic product, logic negation and Ex-OR operations were investigated. The utilizing of these operations for mathematical description of frequency multiplying is shown as the example of application of Π(x) function. Moreover section deals with the problem of rectangular function Π(x) utilization for description of operation of such logical devices as digital sine wave generators and for nonlinear distortions analyzing in such generators.
Edward Hrynkiewicz
3 Design and Application of the PLD-Based Reconfigurable Devices
Abstract
Theoretical bases of construction and designing of the PLD–based reconfigurable devices, including the new formalized design techniques of construction and dynamic reconfiguration of architecture and structure of digital devices with a high degree of reconfiguration, corresponding with properties of performing algorithms, constructive and technological features PLD, and also tool means of their designing, are presented. Bases of the theory of adaptive logic networks, intended for the solution of a wide class of tasks by direct structural realization of algorithms of processing and direct representation of input data to output data by functional and structural customization for universal components of a network, are developed. Synthesis algorithms of adaptive logic networks on the classes of tasks set are developed. Design techniques of the computer systems with using of the standard CAD PLD (ISE Foundation) are developed. The structure of the reconfigurable computer system with the open library of configuration files for basic parametrical blocks, including the threshold device, Hemming adder, sorting devices, median filters, matrix multipliers etc. are designed.
Alexander V. Palagin, Vladimir M. Opanasenko
4 Application of Multilevel Design on the Base of UML for Digital System Developing
Abstract
In this chapter the features of image generation and performing systems’ design are analyzed. Estimation of complexity of the standard rendering pipeline is done. The architectural decisions and algorithm approaches for the real-time rendering systems’ creation are discussed. Adaptation of a multilevel designing method of the built-in systems with realization of separate modules on reconfigurable devices, based on application of architecture operated by models and the unified modeling language, is offered. The graphical application of the modified method is shown.
Raisa Malcheva

Digital Design with Programmable Logic

Frontmatter
5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs
Abstract
The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMBs). Existing methods do not ensure effective utilization of the possibilities provided by such modules. The problem of efficient mapping of combinational and sequential parts of design can be solved using decomposition algorithms. The main question of this paper is the application of decomposition based methods for efficient utilization of modern FPGAs. It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs. Finally we present results of the experiments, which evidently show, that the application of functional decomposition algorithms in the implementation of typical signal and information processing systems greatly influences the performance of resultant digital circuits.
Mariusz Rawski, Paweł Tomaszewicz, Grzegorz Borowik, Tadeusz Łuba
6 Efficient Technology Mapping Method for PAL-Based Devices
Abstract
The core of a contemporary CPLD device is a PAL-based logic block which consists of a programmable AND matrix and a fixed OR matrix. A new technology mapping method for PAL-based devices based on the analysis of graph of outputs is described. The presented approach uses original method for illustrating a minimized form of a multi-output Boolean function. Graph node represents groups of multiple-output implicants with common output part. The essence of the method is the process of searching for appropriate multi-output implicants that can be shared by several functions. A new method for the description of cascaded feedback connections is presented. The experimental results show that the proposed algorithm leads to significant reduction of chip area used by resulting circuits.
Dariusz Kania
7 Reliable FPGA-Based Systems Out of Unreliable Automata: Multi-version Design Using Genetic Algorithms
Abstract
This chapter introduces the principles of multi-version digital system design and describes the concept of developing a reliable and robust system out of unreliable parts. We started with the state of the art in the area of multi-version design and explore the motivations for using different approaches to development of digital projects. A few techniques to manage design diversity for FPGA-based systems are proposed. These techniques are based on the use of genetic algorithms (GAs), and partially correct and partially definite automata obtained with GAs. Finally, we suggested GA-based method of multi-version fault-tolerant systems synthesis and discuss case-study for on-board device implementation.
Nataliya Yakymets, Vyacheslav Kharchenko
8 Synthesis of Compositional Microprogram Control Unit with Dedicated Area of Inputs
Abstract
The chapter is devoted to CMCU optimization, based on the modification of the microinstruction format. Proposed modifications are intended to eliminate code transformers from the CMCU and reduce the hardware amount of circuits used in the FSM for the microinstruction addressing, as compared with the CMCU basic structure. The reduction of the hardware amount is achieved at the cost of increasing the number of cycles needed for the execution of the control algorithms, and in some cases also at the cost of increasing control memory size.
Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, Alexander Miroshkin
9 PeNLogic – System for Concurrent Logic Controllers Design
Abstract
In the paper the CAD system dedicated for modeling, verification, and synthesis of concurrent controllers modeled by interpreted Petri net is presented. Petri net model can be prepared as graph or as textual form. Controllers specified by Petri nets can be analyzed and implemented using method suitable for such model. For verification of Petri net another part of system is used. Moreover, the results of verification are decomposition of net into several communicating state machines (as finite state machines, FSMs). After verification it is possible to transform Petri net model into HDLs model (VHDL and Verilog) and alternatively into EDIF or XNF netlist format. Such prepared models are also simulated and synthesized using other academic or commercial CAD systems. The system has been developing at University of Zielona Góra. Development of new methods of modeling, verification and synthesis has been contributed to make an attempt the new integrated version of the system. In addition, using of Java environment gives opportunity to work out the system that is platform independent.
Marek Węgrzyn, Agnieszka Węgrzyn

Testing, Modeling and Signal Processing

Frontmatter
10 Methods of Signals Processing in Radio Access Networks
Abstract
This article considers optimum stochastic methods of radio signal processing, including parameter assessment tasks and management of parameters of receiving and transmitting devices. Such tasks are formed by state variable methods using Kalman-Bucy optimum recursive procedures. It’s recommended to solve the management problems basing on the division theorem. The article gives analysis of steadiness and efficiency of state and management assessment procedures in steady-state and unsteady-state conditions. It gives recommendations regarding the choice of parameters and efficiency of processing devices taking into account statistics of signals and constraints attributable to certain telecommunication technologies. It analyzes a proposal, within which recursive procedures are used efficiently. The main tasks are united on Multiple-input/Multiple-output (MIMO) principle and are aimed at solving the access problems in mobile communication networks, Wi-Fi and Wi-Max systems, etc. Such tasks include: space-time encoding, multipath effect reduction, radio link power improvement, interference effect reduction, adaptation to channel parameter changes and current signal interference situation, possible repeated use of frequencies.
Vladimir Popovskiy
11 Recursive Code Scales for Moving Converters
Abstract
The methods of construction of recursive code scales (RCS), and also algorithms of placing on a scale of reading out elements (RE) are considered, results of research of correcting possibilities of such scales are shown. RCS for synthesis of drawing of an information path of a scale of sequence have received the name pseudo-random (PRCS) and composite code scales (CCS). Offered scales can be applied as the coded element in moving converters. Recursive scales at the expense of use in them of only one information code path more technologically traditional scales, code paths (CP) which are carried out, as a rule, in an ordinary binary code or in the Gray code. Thus, RCS allows only at the expense of redundancy introduction on number of reading out elements without use of additional control paths to form the codes which are correcting and (or) finding out errors of reading.
Alexander Ojiganov
12 Infrastructure Intellectual Property for SoC Simulation and Diagnosis Service
Abstract
The models and methods for creating Infrastructure Intellectual Property (I-IP) service for the functionalities System on Chip (SoC), which has a minimum set of the real time Built-In Self Test (BIST) tools, are proposed in this chapter. The means I-IP provide an opportunity to services: fault modeling and simulation for the functional primitives to evaluate the test quality and to build Fault Detection Table (FDT); diagnosis of a given defects search depth in the SoC; repairing embedded memory functionality, by using spare row and column components. High performance deductive-parallel fault analysis method for building FDT and tests quality assessment is offered. Algebra logical methods of fault diagnosis and embedded memory repair by synthesis Disjunctive Normal Form (DNF) completing all decisions for diagnosis SoC functionalities in the real time are represented.
Vladimir Hahanov
13 Evolutionary Test Generation Methods for Digital Devices
Abstract
In this chapter, we will discuss how evolutionary methods can be used for test generation of digital circuits. In present time it is strongly investigated the new direction in theory and practice of artificial intelligence and information systems – evolutionary computations. This term is used to generic description of the search, optimizing or learning algorithms, based on some formal principles of natural evolutional selection, which are sufficiently applied in solving various problems of machine learning, data mining, databases etc [1]. Among this approaches following main paradigms can be picked out: genetic algorithms (GA), evolutionary strategy (ES), evolutional programming (EP), genetic programming (GP). The differences of these approaches mainly consist in the way of target solution representation and in different set of evolutional operators used in evolutional simulation. Classical GA uses the binary encoding of problem solution and basic genetic operators are crossover and mutation. In ES solution is represented by real numbers vector and basic operator is mutation. EP uses FSM as solution representation and mutation operator. In GP problem solution is represented by program, crossover and mutation operators are applied. Now this classification is enough relative and interaction of basic evolutionary paradigms each other takes place.
Yuriy A. Skobtsov, Vadim Y. Skobtsov
Backmatter
Metadaten
Titel
Design of Digital Systems and Devices
herausgegeben von
Marian Adamski
Alexander Barkalov
Marek Węgrzyn
Copyright-Jahr
2011
Verlag
Springer Berlin Heidelberg
Electronic ISBN
978-3-642-17545-9
Print ISBN
978-3-642-17544-2
DOI
https://doi.org/10.1007/978-3-642-17545-9

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