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Erschienen in:
2011 | OriginalPaper | Buchkapitel
12 Infrastructure Intellectual Property for SoC Simulation and Diagnosis Service
verfasst von : Vladimir Hahanov
Erschienen in: Design of Digital Systems and Devices
Verlag: Springer Berlin Heidelberg
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The models and methods for creating Infrastructure Intellectual Property (I-IP) service for the functionalities System on Chip (SoC), which has a minimum set of the real time Built-In Self Test (BIST) tools, are proposed in this chapter. The means I-IP provide an opportunity to services: fault modeling and simulation for the functional primitives to evaluate the test quality and to build Fault Detection Table (FDT); diagnosis of a given defects search depth in the SoC; repairing embedded memory functionality, by using spare row and column components. High performance deductive-parallel fault analysis method for building FDT and tests quality assessment is offered. Algebra logical methods of fault diagnosis and embedded memory repair by synthesis Disjunctive Normal Form (DNF) completing all decisions for diagnosis SoC functionalities in the real time are represented.