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Journal of Electronic Testing

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23.02.2018

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells

verfasst von: Freddy Forero, Jean-Marc Galliere, Michel Renovell, Victor Champac

Erschienen in: Journal of Electronic Testing | Ausgabe 2/2018

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Abstract

Since 22nm technology node, FinFET technology is an attractive candidate for high-performance and power-efficient applications. This is achieved due to better channel control in FinFET devices obtained by wrapping a metal gate around a thin fin. In this paper, we investigate the detectability of bridge defects in FinFET based logic cells that make use of Middle-Of-Line (MOL) interconnections and multi-fin and multi-finger design strategies. The use of MOL to build the logic cells impacts the possible bridge defect locations and the likelihood of occurrence of the defect. Some defect locations unlikely to appear in planar CMOS now become more likely to occur due to the use of MOL. It is shown that these defects are difficult to be detected. The detectability of bridge defects has been analyzed for gates with different drive strengths and fan-in, and also extended to the different type of gates. A metric called Bridge Defect Criticality (BDC) is used to identify the most harmful bridge defects. This metric depends on the degree of detectability and likelihood of occurrence of a bridge defect. More design and/or test effort may be dedicated to those defects with higher a value of the BDC metric to improve product quality.

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Titel: Detectability Challenges of Bridge Defects in FinFET Based Logic Cells
verfasst von: Freddy Forero
Jean-Marc Galliere
Michel Renovell
Victor Champac
Publikationsdatum: 23.02.2018
Verlag: Springer US
Erschienen in: Journal of Electronic Testing / Ausgabe 2/2018
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI: https://doi.org/10.1007/s10836-018-5714-0

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