Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices

As the complexity of Systems-on-Chip (SoC) is growing, meeting real-time requirements is becoming increasingly difficult. Predictability for computation, memory and communication components is needed to build real-time SoC. We focus on a predictable communication infrastructure called the Æthereal Network-on-Chip (NoC). The Æthereal NoC is a scalable communication infrastructure based on routers and network interfaces (NI). It provides two services: guaranteed throughput and latency (GT), and best effort (BE). Using the GT service, one can derive guaranteed bounds on latency and throughput. To achieve guaranteed throughput, buffers in NI must be dimensioned to hide round-trip latency and rate difference between computation and communication IPs (Intellectual Property). With the BE service, throughput and latency bounds cannot be derived with guarantees. In this chapter, we describe an analytical method to compute latency, throughput and buffering requirements for the Æthereal NoC. We show the usefulness of the method by applying it on an MPEG-2 (Moving Picture Experts Group) codec example.

We discuss why performance verification of systems on chip (soc) is difficult, by means of an example. We identify four reasons why building socs with predictable performance is difficult: unpredictable resource usage, variable resource performance, resource sharing, and interdependent resources. We then introduce the concept of a service, aiming to address these problems, and describe its advantages over “ad-hoc” approaches. Finally, we introduce the Æthereal network on chip (noc) as a concrete example of a communication resource that implements multiple service levels.

Systems-on-Chip (SoC) of the new generation will be extremely complex devices, composed from complex subsystems, relying on abstraction from implementation details. These chips will support the execution of a mix of concurrent applications that are not known in detail at chip design time. These SoCs require a significant degree of programmability to configure both the set of functions that must execute as well as the structure of the dataflow between these functions. To ease the programming effort multiprocessor computers have employed cache coherent share memory for decades, abstracting the average programmer from system complexity issues such as multiple processors and memory hierarchies. Memory coherency in multiprocessor computers has a history of decades, and has proven to be an indispensable abstraction from system complexity towards the application programmer. This chapter describes a next generation SoC for the consumer electronics domain (e.g. audio/video, vision, robotics). It features heterogeneous multiprocessor subsystems with a snooping cache coherence protocol, combined in a system with distributed memory employing a directory coherency protocol. It is explained why and how the coherent memory model is indispensable for implementing both data transport and synchronization for multi-tasking streaming applications in distributed memory systems.

Dataflow analysis techniques are key to reduce the number of design iterations and shorten the design time of real-time embedded network based multiprocessor systems that process data streams. With these analysis techniques the worst-case end-to-end temporal behavior of hard real-time applications can be derived from a dataflow model in which computation, communication and arbitration is modeled. For soft real-time applications these static dataflow analysis techniques are combined with simulation of the dataflow model to test statistical assertions about their temporal behavior. The simulation results in combination with properties of the dataflow model are used to derive the sensitivity of design parameters and to estimate parameters like the capacity of data buffers.

The signal processing for TV is changing rapidly at this moment. The classical analog broadcast is being replaced by digital broadcast, CRTs are being replaced by Matrix displays, and the convergence between PC and CE introduces PC standards and applications in the TV domain. Collectively, these changes have a big impact on the signal processing architecture of a TV. Signal processing has always been a field of competence for Philips. To keep a leading position in this area, Philips has developed the Nexperia Home Platform. This platform is a mix of both hardware (HW) and software (SW). SW gives the flexibility needed for configuring such a platform for a range of products. HW allows cost-effective implementations of compute intensive signal processing. This chapter discusses the required SW streaming infrastructure in such a platform. A SW streaming infrastructure is an enabler to fulfill the streaming requirements, and to provide the required flexibility in the platform to come to a cost-effective solution. We will explain requirements on the streaming infrastructure in a platform by looking at Hardware/Software (HW/SW) tradeoffs, real-time requirements constraints, and the complexity of controlling signal processing. This chapter will take the examples from the TV and Storage domain.

The Robocop project defines an open, component-based architecture for the middleware layer in high-volume consumer electronic products. This architecture supports component trading, dynamic upgrading and extension of products in the field, and robust and reliable operation. The architecture consists of a development framework, an execution framework and optional download and resource management frameworks. The core of the architecture is the component model, which is defined at two levels. At the development level, a component is defined to be a collection of models and the relations between these models. These models allow system builders to reason a-priori about systems composed from the components. At the execution level a binary component model has been defined, combining elements of Object Management Group (OMG), Common Object Request Broker Architecture (CORBA), Microsoft's Component Object Model (COM), and Philips' Koala. Key elements of the executable component model are explicit dependencies, dynamic third party binding, and a well-defined lifecycle that includes explicit interaction points with the resource management framework.

More and more consumer devices in future homes will be inter-connected via wireless networks. However, due to their limited and fluctuating bandwidth and susceptibility to interference, the transport of content with real-time characteristics, such as video, is a problem. This paper presents a Quality-of-Service (QoS) architecture framework to achieve smooth, undisturbed video streaming over wireless networks, where still sufficient output quality is achieved even when the network conditions deteriorate. Our solution combines two techniques to address wireless video streaming issues, namely scalable video coding and network adaptation. The feasibility of our framework is proven by implementing receiving and decoding Signal-to-Noise Ratio (SNR)-scalable video streams on a resource-constrained consumer terminal platform. Extensive visual experiments and numerical measurements show that it is possible to achieve smooth output video, even with heavy interference from other electronic devices.

Wireless networking technology will interconnect the consumer devices in the future homes. The capacity of the wireless technology is just sufficient to transport one or two high quality videos. When the wireless transmission is perturbed by the switching on of a microwave or a Bluetooth telephone, many artifacts appear on the screen during the display of the video. Two “scalable video” techniques are proposed to remove the artifacts. These techniques have a different effect on the quality of the video as perceived by the user. An experiment is presented which evaluates the effects of the two techniques dependent on their settings. Conclusions are drawn on the best setting dependent on the operational transmission conditions and the transmitted video.